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Friday, November 5, 2021

Making Measurements with the V3 Curve Tracer

This post will describe a number of measurements that can be made with the V3 Curve Tracer, described in another post. More measurements will be added or maybe changed so keep an eye out for additions and changes.

The instrument is not finished, we're still testing and will be improving or changing things or even adding features. We have a few revisions for circuit boards under way, but this is almost as good as it gets. For details of the design, look at the following posts:

The building of the first version, actually a working prototype with a detailed Theory of Operation.
https://www.paulvdiyblogs.net/2017/

There is also a description of the second generation based on the first prototype. This is a fully functional CT but has some problems and shortcomings that we're addressing in V3.
https://www.paulvdiyblogs.net/2021/03/building-curve-tracer-v2.html

The design process of the V3 CT.
https://www.paulvdiyblogs.net/2021/11/making-meassurements-with-v3-curve.html

 

Reference Documents

I will try to follow a number of documents as the guideline for testing since several of you will have some experience with the Tektronix 577 & 576 workhorses. These instruments are still used in many workshops, labs and classrooms so chances are you have used them. Unfortunately, these instruments are dying of age and cannot be fixed anymore due to unavailable replacement parts. 

We cannot do all measurements these benchmark instruments can make with our CT, but we can do many.

There are a number of documents that I used as guidelines for these measurements. They are listed here:

Tektronix 577 Device Testing Techniques:
https://w140.com/Tektronix_577_DeviceTestingTechniques.pdf

Understanding Power Transistors Breakdown Parameters
https://www.onsemi.com/pub/Collateral/AN1628-D.PDF

Bipolar Transistors, Terms used in data sheets:
https://toshiba.semicon-storage.com/info/docget.jsp?did=63511&prodName=2SA1225 

 

Making measurements

For the time being, use this Front Plate design as a guideline for using and setting-up the CT.
Click on the picture to see a larger size.
 

 
Note: After finishing the layout, I found that the special TO-220/TO-92 test sockets that are supposed to be on the left and right of the DUT section, are no longer available. I have found a replacement but will wait for another board turn before we change the layout again.
 
 
Below I will describe some measurements of devices to see how well the CT behaves and if we can find things we need to understand, fix or ignore. This is a work in progress and I will add more and more measurements while we test the capabilities of the instrument while hunting for problems or weaknesses.
 
So with what we have now, and with some of the limitations still there, what can we do already?

1. A few generic measurements

Setup to profile a small signal BJT

Let's look at the venerable 2N3904, probably the most popular small signal NPN BJT. This is a 40V VCEO transistor that can handle an IC of 200mA and has an hFE (beta) between 40 minimum (at 100uA IB and VCE of 1V) and typical 300 (at 1mA IB and VCE of 1V), which is a very large spread. I suggest you look at the datasheet for reference.
 
So how do we use the Curve Traces to look at this device? 
For reference, look at the face plate above. I'll do the setup going from left to right. 
But first, turn the Sweep Voltage to 0% and set the DUT selector to the off position. 
It's good practice to do this before every start of a new setup or measurement. It's a good way to prevent DUT losses.

Step Delay should be off. Offset should be off. Select the N Polarity.
Select the BJT mode and select 7 steps. Set the Step Base current output at 100uA/step.
 
Plug the transistor in the left or right DUT socket.
 
Set the Current Limit to 100% (no output). 
Set the current range to x0.05 to create a maximum current of 2A x 0.05 = 100mA. 
Set the X-Amp to x10, this is for small signal devices. Higher powered devices will need the x1 setting.
Set the Sweep Voltage Range to 35V. 
 
On the DSO, select the X-Y Time base. 
Adjust the sampling mode of the DSO to a lower setting, I use 70KPoints to reduce the noise.
Set CH1 to a Ratio of 10x so the readout is 1:1 with the Sweep Voltage. Select a limited bandwidth to reduce noise. I use the lowest setting of my DSO; 20MHz.
Set CH2 to 20mV/Div, 20MHz bandwidth and a Ratio of 0.01x to make the readout 1:1, meaning that 1mV represents 1mA.

Adjust the vertical positions so the dot is at the cross-hairs of the first division vertical, and the first division horizontal (the 0V and 0mA origin).

Select the DUT position to apply power to the transistor. Turn up the Sweep Voltage to have 5 divisions horizontally, which will be a Collector voltage of 10V.

You should now have the following display or close to it:



So what do we see here?
The first step of the cycle is at 100uA. We see that this results in about 22mV. The 22mV represents an IC of 22mA so the hFE or beta will be about 22mA/100uA or 220. 
When I measured this transistor in my little China test device, it showed a beta of 225 with a VCE of 5V, which is close enough and in agreement.
However, what this little tester does not show is that the beta changes quite dramatically with higher steps or Base currents and also with different VCE's at these higher IB's. This is caused by the Early Effect (https://en.wikipedia.org/wiki/Early_effect).

So what happens when we lower the Base current?
When we lower the Base current to 10uA/Step, and set the V/Div to 2mV, we get the following result:


Note that the distribution per step is now much more uniform, and the lines stay more horizontal. This is a much better operating area for this transistor. The hFE is now 10uA Base current and 1.8mV or 1.8mA which is about 180, so it's dropping.

We can go even lower, to 1uA/step:
 

Now we're getting down into the noise and the current CT rig capacitance is starting to play a role as we showed in the Version 3 Blog. To reduce this phenomena, I lowered the base frequency of the triangle/steps to about 155Hz and now the display is OK with only a little blossoming.
The hFE at these step currents is now much lower, 2uA for the second step that shows 200uV, so a gain of only 100.

When we raise the Base current to 1mA/step, we are getting into the maximum Collector current area of 200mA.


Luckily, we set the maximum current to a limit of 100mA, because without it, we could have killed the transistor due to thermal stress. If you use your fingers on the device, you will notice that it will get warm, but with this current limitation, there is no harm done to it.
 
We can measure the device with a higher current limit, but in order to reduce the thermal stress, we need to activate the Step Cycle Delay function, and set that to the maximum.
Now we can select a higher current range by changing the range from 0.5x to 0.1x, which at a maximum current of 2A will now be 200mA which is the limit of the 2N3904.  


The transistor could easily go beyond the 200mA, but it is Current Limited, and does not get overly hot. The display does not drift upwards due to the thermal stress that increases the beta, which is a sure sign that the device is getting into a thermal run-away that could lead to its quick heat-stroke death.

Measuring the maximum Collector voltage

 
This is not the "official" method but shows a quick-and-dirty way. The 2N3906 is specified with a maximum VCE0 of 40V, lets see what happens when we raise the voltage. We set the Base current back to 10uA/Step and slowly raise the Sweep voltage to 55V.

 

Beyond 40V, the transistor is getting near the breakdown voltage (VCBEO) and the Collector current skyrockets due to the avalanche effect. This is a measurement you should make very carefully. The VCBEO specification for this transistor of 40V is met. 

Note
Because the Collector current goes up fast due to the avalanche effect (breakdown and potentially even punch through), setting the proper current range and setting the current limiter is very important because the device can easily get damaged or even destroyed before you know it.
 

Profiling a diode

 
I'm using the well known 1N4148 diode as an example. The diode gets connected between the E and C connections in the ZIF socket. Connect the Anode to C and the cathode to E. We set the current range to x.05 and the CL at 25%. Start with the 35V range for the forward voltage. Set the Sweep voltage to 0%.
Set the DSO hor. channel to 200mV/Div and the vert. channel to 1mV/div.
Set the polarity to N.
Slowly turn up the sweep voltage until current starts to flow.


The voltage when the device starts to conduct can be seen here and is at about 500mV and goes up to about 750mV with a higher current. The diode has specifications for different forward voltages at various currents. The specification says between 0.62V and 0.72V at 5mA. That is what we see here as well.

Reduce the sweep voltage and select the 200V range. Set the hor. channel on the DSO to 50V/Div Change the polarity to P to reverse the voltage to the diode. Slowly turn up the sweep voltage until there is current flowing again, signalling the maximum reverse voltage. 



The reverse voltage is about 180V, the specification says 100V. Check!

Profiling a Zener diode

 
I'm using a generic 10V 1/4W Zener diode. Set the voltage range back to 35V, and set the hor. DSO channel to 200mV/Div. Select the N polarity and connect the Zener diode with the Anode to C and the Cathode to E. Set the current range to x.05 and the CL at 25%. Set the sweep voltage to 0%.
Select the DUT socket and slowly turn up the sweep voltage until current starts to flow.

The forward voltage is about 680mV at 6mA.


Reduce the sweep voltage and switch the polarity to P to reverse the voltage.
Slowly increase the sweep voltage until current starts to flow.

The Zener voltage, or reverse voltage is exactly 10V at 1mA but increases slightly to 10.1V at 7mA.

Further measurements can be made by increasing the current and see what the Zener voltage does.

Set the vert. channel to 20mV/div. and slowly increase the current by adjusting the CL.



At 100mA, the Zener voltage is now at least 10.2V, something to keep in mind when you design circuits.

 

Profiling a Schottky diode

I'm using the popular 1N5819 Schottky diode.


 As to be expected with a Schottky diode, the forward voltage is about 350mV at 40mA.
 
 

 
The reverse voltage is limited to about 54V. 

 

Profiling LED's



I'm using a selection of 3mm LED's with different colors to see what the difference in forward voltages is for the different colors, and also what the brightness levels are with the same current.



This is a white LED, the forward voltage is 3.4V at 40mA and it is by far the brightest of all.



This is a red LED and the forward voltage is 2.2V at 40mA, and it is very bright.


This is a blue LED with a forward voltage of 3.4V at 40mA, it is very bright.


This is a green LED with a forward voltage of 2.2V at 40mA, it is the least bright of all. Note that this has a small amount of forward voltage change per current, which is why the green, red and also the yellow LED's can be used in simple constant current circuits.


This is a yellow LED with a forward voltage of 2.3V at 40mA, it is also very bright.
 

Testing a capacitor for leakage

This is a new test after we added the DC mode for the supply.
In the following test I'm using two 1,000uF/100V 85 degrees C capacitors in series at allow the testing at 200V. These capacitors were actually used in my first prototype, and are probably not of the best quality. The manufacturer is REC.


At about 150V, the leakage current starts to go up and reaches about 4.2mA at 180V.

I also tested a 1uF/450V film capacitor. It showed the following results.
 
 
No leakage. We do not show a "dot" because there are glitches coming from the triangle generator on the signal. This results in this vertical line. It is more prominent here than in the previous measurement because the vertical sensitivity is doubled. The glitch is probably coupled into the XY amp due to the setup we use with the 6 10x10 boards and the long interconnect leads. We'll have to revisit this with the new Front Panel layout that Mark is currently working on.


2. Device Testing Techniques on a Tektronix CT

 
I'm using a number of measurements described in the Tektronix 577 Device Testing Techniques Handbook, available here:
I'm using this information as my guideline, just to see if and how we can do the same tests with our CT.

Testing a BJT transistor

Test 1: Measuring the Collector-Emitter breakdown voltage V(BR)CEO

This is actually the preferred method to measure the C-E breakdown voltage as it is referenced in the textbooks.
 
The Emitter and Collector are in the ZIF socket while the Base is left floating (not connected or open - this is the O in CEO). The Sweep Voltage can be in the 75V or 200V range, with the current range at x0.02 and the CL adjustment at 30%. The X-amp is set at X10 to have more sensitivity, and the DSO vert. channel is set to a 0.001 multiplier ratio to keep the readout in mV compatible to the IC current in mA. Start with a minimal Sweep voltage. Select the DUT and slowly raise the Sweep voltage until the current shoots-up rapidly. You can raise the CL limit a bit to get a better picture.



In this case, the breakdown VCEO is at about 60V, while the specification is for 40V.

Test 2: Measuring the Emitter-Base reverse breakdown voltage (V(BR)EBO

 
In this test, we will connect the Base of the transistor to the Emitter socket (grounded Base) and connect the Emitter of the transistor to the Collector socket. Leave the Collector lead of the transistor floating (not connected).
Set the voltage range to 35V and set the current range to x.02, set the CL adjustment to 30% and the Sweep voltage to minimum.
Slowly increase the Sweep voltage until the current shoots up which shows the breakdown voltage.


The V(BR)EBO is at about 7.8V, while the specifications is listed at 6.0V so the device passes this test.

Test 3 : Collector Cutoff Current ICEV or ICEX

We need to investigate how and even if, we can do this measurement with our CT. 
Stay tuned...
 

Test 4 : Collector-Base Breakdown Voltage V(BR)CBO

 
With this test we measure the point when excessive current begins to flow between the Collector and the Base with the Emitter terminal open. The Collector of the transistor is connected to the Collector connection on the ZIF socket, The Emitter is not connected and the Base of the transistor is connected to the Emitter socket of the ZIF (grounded Base). The Sweep voltage range is 200V and the current range x0.02. CL at 80% and the Sweep voltage at minimum.
Slowly increase the sweep voltage until a Collector current starts to flow. You can adjust the CL to a better display.


The V(BR)CBO is measured at 90V, while the specification is at 60V.

Test 5 : DC Forward Current-Gain (DC Beta or hFE)

 
The DC forward gain is the ratio of the DC Collector current to the DC Base current.
We cannot really follow the measurement as described in the handbook because we do not have a "no" step setting, our minimum is one step. We also don't have an offset multiplier function. We have an offset, but it is not calibrated and cannot function as a step setting multiplier. The reason is that I decided against using a 10-turn potmeter with a scale for the offset. Adding an offset multiplier function would add more complexity to the circuit, too much to the price, and take up too much room on the Front Panel.
 
We can still do the measurements, but we will have to use a slightly different approach by setting the Base current such that we get close to the specified current as listed in the specifications.
For the 2N3904, the hFE or DC Current Gain with a VCE of 1V is:
  • IC = 0.1 mA, hFE is 40 min.
  • IC = 1.0 mA, hFE is 70 min. 
  • IC = 10 mA,  hFE is 100 min. 300 max.
  • IC = 50 mA,  hFE is 60 min.
  • IC = 100 mA, hFE is 30 min.
You would normally only do one measurement that is close to the intended application, but I will do all of them here.
 
If we setup the CT with a VCE of 1V, and select only one step, we can adjust the step current such that we get close to the required IC. In the case of an IC of 0.1 mA, we can set the Vert. channel of the DSO to 100 uV/Div, and adjust the Base current so we get close to a deflection of 1 division or 0.1mA. (100uV)
 



The IC is about 80uA. This was obtained with a Base current of 1uA/Step, so the hFE should be 80uA IC / 1uA IB or 80. Significantly higher then the specified minimum of 40.
 
Of course you can use different V/Div settings to have a better view with more divisions, but I purposely selected the same V/Div as the required current to make the calculations more apparent.
 
In the case of an IC of 1 mA, we can set the Vert. channel of the DSO to 1mV/Div, and adjust the Base current so we get close to a deflection of 1 division or 1mA. 
 


The IC is about 1.5 mA. This was obtained with a Base current of 10uA/Step, so the hFE should be 1.5mA IC / 10uA IB or 150. Significantly higher then the specified minimum of 70.

To measure the hFE for a 10mA IC, we set the V/Div to 10mV/Div and adjust the Step output until we have close to 1 div.


This was obtained with a Base current of 50uA so the hFE is 10mA/50uA or 200 and this is right in the middle of the specification of 100 min and 300 max.


With an IC of 50mA, we set the V/Div to 50mV and adjust the Step current to get close to 1 division.


This was obtained with a Base current of 500uA so the hFE is 50mA/500uA or 100, a little better than the specification of 60.

The 100mA specification was measured with a V/Div of 100mV, and adjusting the Base current to get a deflection of 1 division.


In order to get a flat line for the Base current, I had to increase the sweep voltage a little. The Base current needed was 2mA so the hFE is 100mA/2mA or 50, well above the minimum of 30.

Test 6 : Collector-Emitter Saturation Voltage VCE(SAT)

 
The VCE saturation voltage is the value of the Collector voltage below which an increase in specified Base current cannot cause an increase in Collector current anymore.

The VCE(SAT) is specified at 200mV with a Base current of 1mA. 
We set the number of steps to one, 1mA/step, 35V range, current range x1. Step Delay on and at maximum to protect the transistor from over-heating. Offset positive and initially at minimum. Sweep voltage at 1.5-2V. On the DSO, set the Hor. channel to 200mV/Div, and the Vert. channel to 50mV/div.
The following display should be the beginning situation:
 
 
 
Slowly increase the offset until you have a diagonal but straight line.
 
 
This is the point where no further increase of the Base offset voltage will increase the Collector current. The VCE(SAT) is at about 250mV while the specification is for 200mV.

I think this is what the Tektronix engineers meant to measure, but I could be wrong.

This concludes all the measurements out of the handbook for a Bipolar Transistor, and with some differences, and with one exception, we can do them all.
 
More measurements for other devices could be added later.
 
 

3. Testing transistor breakdown parameters

Apart from the measurements we just saw earlier, described in the Tektronix handbook, there are a lot more we can make to profile a BJT.
I'm going to follow a list of measurements as they are described in the ON semi AN1628/D Application note for high power BJT's. The same principles apply to small signal ones, like the 2N3904.
A link to the app note is listed above.
The nice thing about this App Note is that they included a little schematic of how the DUT is wired for the various measurements and tests.
 
I'm going to follow their measurement order starting on page 12.
 

Breakdown Voltages

BV stand for Breakdown Voltage. This is also shown as V(BR)CEO in some data sheets.
Set the output selector to Tri for Triangle Sweep Voltage waveforms.

BVCEO 

This measurement is for reverse Collector to Emitter voltage, with the Base open, under a given Collector current bias.
 
We already did this measurement above, but here it is again, just for completeness. 

Connect the 2N3904 to the ZIF socket with only the C to C and E to E leads connected, leave the Base lead open, so flopping in the breeze.
Set the voltage range to 75V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current. Set the Sweep voltage to minimum.
Set CH1 to 10V/Div and CH2 of the DSO to 200uV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow.
The 2N3904 shows this to happen at 60V, the specification is for 40V.


NOTE
What can happen when you make this measurement is a case of a snap-back breakdown, which is common in this configuration. The Base is open and the avalanche current (also called first breakdown) is reaching a critical Base current to cause the device to enter a second breakdown at a lower voltage. The voltage at the Base will depend on the level of current limiting and the amount of resistance from Emitter to GND. I have measured up to 50V on the floating Base lead with a DMM myself.
This effect is described in the App Note on page 4, Second Breakdown.
 
We also found that the breakdown or even the punch-through event can turn on the Fault indicator LED because the protection circuits for the Step Gen are activated as a result of severe glitches generated by the DUT. This event will cause glitches on the Step Gen supply rails and that trips the Fault circuitry and and in turn switches the Collector voltage off for a few Milli-seconds and then release it again. At this moment, all our fixes showed no real results so we have to wait for the new layout and see if this fixes the problem. The only way to make this measurement now is by disconnecting the Fault signal from the Sweep supply.
 

BVCBO

This is the reverse Collector to Base voltage, with the Emitter open, under a given Collector current bias.
 
Connect the 2N3904 to the ZIF socket with the Collector to C and the Base to the E contact, leave the Emitter lead open, so flopping in the breeze.
Set the voltage range to 75V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 20V/Div and CH2 of the DSO to 200mV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow.
The 2N3904 shows this to happen at 140V, the specification is for 60V.


BVCER

Reverse Collector to Emitter voltage, the Base connected to the Emitter with a low Ohm resistor, under a given Collector current bias.


Connect the 2N3904 to the ZIF socket with the Collector to C, the Base with 100 Ohm to E and the Emitter to E. Keep the resistor very close to the 2N3904 and use short leads.
Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 20 or 50V/Div and CH2 of the DSO to 200uV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow.
The 2N3904 shows this to happen at 125V, there is no specification in the data sheet.
 

The current is limited at 400uA.

BVCES

Reverse Collector to Emitter voltage, the Base shorted to the Emitter, under a given Collector current bias.

Connect the 2N3904 to the ZIF socket with the Collector to C, the Base and the Emitter to E.
Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 20V/Div and CH2 of the DSO to 200uV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow.
The 2N3904 shows this to happen at 140V, there is no specification in the datasheet.
 
 

 

BVCEX

Reverse Collector to Emitter voltage, with a reverse Base to Emitter bias, under a given Collector current bias.
 
We do not have a calibrated offset voltage so this measurement could be made, but with an external supply.
  
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base to a negative variable DC supply, the positive supply connector to the Emitter and the Emitter to E. 
 

BVCEY

Reverse Collector to Emitter voltage, with a forward Base to Emitter bias, under a given Collector current bias.
 
We do not have a calibrated offset voltage so this measurement could be made, but with an external supply. 

Connect the 2N3904 to the ZIF socket with the Collector to C, the Base to a positive variable DC supply, the negative supply connector to the Emitter and the Emitter to E. 

BVEBO

Reverse Emitter to Base voltage, with the Collector open, under a given Emitter current bias.

Connect the 2N3904 to the ZIF socket with the Emitter to C, the Base to E and the Collector open.
Set the voltage range to 35V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 2V/Div and CH2 of the DSO to 500uV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow.
The 2N3904 shows this to happen at 8.2V, the specification is 6V.
 
 

Leakage Currents

These measurements are the domain of the DC "Sweep" Voltage. Set the voltage selector to DC.

Note that with our CT, and many others, the leakage current measurements are made in the Collector connection to the positive supply, not in the Emitter connection to the negative supply. In the DC mode, you only see a "dot" representing the voltage on the DSO.

ICEO

Collector to Emitter current under reverse Collector to Emitter voltage, Base open.
 
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base open and the Emitter to E.
Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 20V/Div and CH2 of the DSO to 1mV/Div.
Power the DUT and slowly increase the DC Voltage until current starts to flow.
 
 
The 2N3904 shows this to happen at 82V, when the "dot" changes to a vertical line. The vertical line means that the current is fluctuating wildly. There is no specification for this test in the data sheet.
The amount of current here is about 3.3mA but can be further increased by carefully increasing the CL adjustment.
 
NOTE
What can happen when you make this measurement is a case of a snap-back breakdown, which is common in this configuration. The Base is open and the avalanche current (also called first breakdown) is reaching a critical Base current to cause the device to enter a second breakdown at a lower voltage. The voltage at the Base will depend on the level of current limiting and the amount of resistance from Emitter to GND. I have measured up to 50V on the floating Base lead with a DMM myself.
This effect is described in the App Note on page 4, Second Breakdown.
 
We also found that the breakdown or even the punch-through event can turn on the Fault indicator LED because the protection circuits for the Step Gen are activated as a result of severe glitches generated by the DUT. This event will cause glitches on the Step Gen supply rails and that trips the Fault circuitry and and in turn switches the Collector voltage off for a few Milli-seconds and then release it again. At this moment, all our fixes showed no real results so we have to wait for the new layout and see if this fixes the problem. The only way to make this measurement now is by disconnecting the Fault signal from the Sweep supply.
 
If not, you will see something like this on the DSO:
 

There is no "dot" representing the DC voltage, because it switches between zero and the set voltage.
 

 ICBO

Collector to Base current under reverse Collector to Base voltage, Emitter open
 
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base to E and the Emitter open.
Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 50V/Div and CH2 of the DSO to 1mV/Div.
Power the DUT and slowly increase the DC Voltage until current starts to flow and the dot goes up. If the limiting stops the voltage from going up, increase it a little.

 

 
The 2N3904 shows this to happen at 150V. The current is limited by the CL at 2mA, but can now be further increased. There is no specification in the data sheet.
 

ICER

Collector to Emitter current under reverse Collector to Emitter voltage, Base connected to Emitter by a low Ohm resistor.
 
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base with 100 Ohm to E and the Emitter to E.
Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to50V/Div and CH2 of the DSO to 1mV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow. If the limiting stops the voltage from going up, increase it a little.

 

The 2N3904 shows this to happen at 125V and at 800uA. The current can now be increased further by the CL. There is no specification in the data sheet.
 

ICES

Collector to Emitter current under reverse Collector to Emitter voltage, Base shorted to Emitter.
 
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base and the Emitter to E.
Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.
Set CH1 to 50V/Div and CH2 of the DSO to 1mV/Div.
Power the DUT and slowly increase the Sweep Voltage until current starts to flow. If the limiting stops the voltage from going up, increase it a little.

 
 
The 2N3904 shows this to happen at 125V, with 1mA. The current can now be further increased by the CL. There is no specification in the data sheet.
 

ICEX

Collector to Emitter current under reverse Collector to Emitter voltage with a reverse Base to Emitter bias.
 
We do not have a calibrated offset voltage so this measurement could be made, but with an external supply. 
  
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base to a negative variable DC supply, the positive connector to the Emitter and the Emitter to E.

ICEY

Collector to Emitter current under reverse Collector to Emitter voltage, with a forward Base to Emitter bias.
 
We do not have a calibrated offset voltage so this measurement could be made, but with an external supply.  
 
Connect the 2N3904 to the ZIF socket with the Collector to C, the Base to a positive variable DC supply, the negative connector to the Emitter and the Emitter to E. 
 

IEBO

Emitter to Base current under reverse Emitter to Base voltage, Collector open.
 
Connect the 2N3904 to the ZIF socket with the Collector open, the Base to E and the Emitter to C.
Set the voltage range to 35V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current but without limiting. Set the DC voltage to minimum.
Set CH1 to 2V/Div and CH2 of the DSO to 500uV/Div.
Power the DUT and slowly increase the DC Voltage until current starts to flow.

 

The 2N3904 shows this to happen at 8.3V. I then increased the CL until there was no more limiting and the dot did no go up any further signalling the maximum leakage current. At the same time, I increased the V/Div to 5mV/Div. The maximum leakage current shown is 10mA.  There is no specification for this test in the data sheet. 

 

4. Profiling a high power BJT

 
Testing a high power BJT like the MJL3281A is a little different in a few aspects.
The MJL3281A is a 260V 15A NPN BJT with an hFE between 45 and 150. 
 
It is one of the transistors we used in earlier Collector/Drain supply versions, most notably in the Version 1b.
 
Because this transistor can dissipate up to 200W, we need to be a little careful.
First of all, I switched the current range to x.5 to allow a maximum current of 1A in the 35V range.
I then started with a Base current of 100uA/step. It produced the following result:
 
 
The hFE stays evenly spread with the Collector voltage and Base currents. The gain is 9mV=9mA/100u is about 90.
If we go to a higher Base current, like 1mA/step, we get the following result:


The device is not current limited, but only shows 3 steps? This is because the Y-output amplifier output is hitting the 24V supply rail. 
 
This is because I did not change the IC current shunt from the X10 to the X1 setting yet. This is in effect a 10X multiplier and this causes the input signal to hit the supply rail of 24V.
The X10 multiplier is intended for small signal devices to avoid low V/Div settings of the scope.
 
You could also reduce the number of steps to avoid that, in this case, we can only allow 2 steps. 
 
With the X1 setting, you also need to change the Y-channel of the scope to a ratio of 0.1X to keep the readout consistent. By also increasing the Current Limiter, we can get the full 7 steps displayed again:
 

 
 
When we go to a much lower Base current, like 10uA/step, we get the following picture:
 

Here we see the dV/dt effect caused by our current configuration in all it's ugly glory. Here is the corresponding Time-Base display:


So how does it behave when we apply the maximum VCE0 of 200V?
I set the Base current to 100uA/step, turned the CL adjustment to 100% and set the current limiter to x1, to have the full 100mA in this range at our disposal.


At higher Base currents, the Collector current is about to shoot up due to the avalanche effect and the device is getting close to the breakdown voltage. The dV/dt effect is more noticeable with this measurement.
Be careful testing the temperature of the device with your fingers, there is 200V on the collector pad. Keep fingers on the plastic! However, with 100mA, it should not get warm. Also, make sure you select the right current setting and use the current limiter to protect the device.
 

5. Profiling a small signal MOSFET

 
I'm using the LP0701 in the TO-92 package, which is a P-channel MOSFET. It has a VGS(th) of -1V, a DSS of -16.5V, an RDS(on) of 1.5 Ohm and an ID(on) of -1.25A. So how do we go about testing that device.
 
First of all, the polarity should be P, and this will take care of all the negative polarities of the specifications. It is also a V(oltage) device, so select FET as the device type. We'll select 7 steps. The VGS(th) is 1V, so we'll select 500mV/step to get over the threshold, and a 10V sweep voltage. 
 
Because a MOSFET can conduct a large current, even though it is considered a small signal device, we set the current range to X.1 for a maximum of 200mA and set the CL to 50% so we have a safe maximum of 100mA. We also need to set the Y-amp multiplier to X1 and change the DSO channel multiplier to 0.1x, not the 0.01x we used for the small signal current devices.
 
Slowly raise the CL limiter to 100%.
 
So what do we see?
 

 
Not what we expected, right? We see only two steps and the rest is current limiting at 200mA. The reason is that with 500mV/step, the device is conducting a lot more current with the higher steps than you would expect from a small signal device.
 
Lower the CL setting first and then switch to a higher current range of X.2 which will be 400mA.
Slowly turn up the current limiter and observe the display. Turn it down quickly to avoid too much heat.
 

This is more like it, but we till can't see the higher steps because of the large Drain current that is limited at 400mA.
 
We need to lower the volts per step, so we'll go down in current. 
At 200mV/step, things start to look a bit more familiar:



 
 
However, we still only see steps 4, 5, 6 and 7. Why? Because step 4 will be at 4*200mV which is the VGS of 1V, when the device starts to conduct so that's the first step we'll see. Steps 1-3 are hidden from view.
How can we look at all the 7 steps? We need to go to an even lower step voltage so now we select 50mV/step to help keep the current in check.
 
We now can use the Step offset feature to put the zero(!) step at the VGS(th) of 1V. We select the negative offset polarity (P-FET) and carefully adjust the offset to display all 7 steps.
You may have to raise the current limit to show all 7 steps without limiting, but turn it down again when you have seen this to keep the device from over-heating.
 
 
 

The zero step is now positioned at a voltage of about 1V, so the steps will further open up the device a step-at-a-time. The beta is increasing with the Drain voltage, something to be aware of. Note that the Drain current is almost at 250mA with step 7. You can use your fingers to keep an eye on the temperature of the device.

To keep the device from over-heating, we can use the step cycle delay function that greatly helps to limit the dissipation. Turn it on, and set it to the maximum. Watch the display and keep your fingers on the device to "feel" the difference.

Let's now see what the Breakdown Voltage (BVDSS) is. This is the voltage at which the reverse-biased body-drift diode breaks down and significant current starts to flow between the Source and Drain by the avalanche multiplication process. Turn up the Drain voltage until the device starts to show this process.



 
At about 20V, you can see that the Drain current is rapidly increasing due to the avalanche effect and is approaching the breakdown voltage. The specification of 16.5V is easily met. The fact that you see oscillation can be part of this particular measurement. The device is getting more and more unstable. 
 
At this voltage level and because the FET is fully conducting, the device will get very hot, so be quick, and be careful. Because of the RDS(on) of only 1.5 Ohm, even the step cycle delay feature will not reduce the thermal heat enough for a long measurement when you use all steps. Make sure you use the right current range and use the current limiter to protect the device from damage or destruction.
 
A more prudent method for determining the VDss Breakdown Voltage is to use only one step, and use the offset feature to just turn the device on, and then increase the Drain voltage to keep dissipation under control.
 

6. Profiling a high power MOSFET

 
One of the power devices I used was out of the small selection of suitable N-MOSFET's we picked for the Collector/Drain supply, the STW6N90K5, a 900V 6A device that has a Vgs(th) of 4V and a Ciss of 432pF.
Select the FET device type.
 
To get a handle on the Gate voltage, you really need to use the offset feature that allows you to set the proper Base step voltage to turn the device on.
 
Here is a screenshot taken with 100mV/Step, 7 steps, 10V and a bit of positive offset to make the zero step already conduct the device.



 The device is getting a tiny bit warm.

To test it with a higher voltage, and keep the dissipation in check, I reduced the number of steps to 4. I used the 75V range with the maximum voltage.


You can see that the gain no longer climbs up after the voltage is at about 40V, this is a much better operating area for this device. Notice the beginning of blossoming of the higher step traces due to the increase in heat.

In the 200V range with maximum voltage, this is the result.


There is current limiting in effect due to the dissipation that I wanted to keep in check, even with a mere 100mA. The device gets hot and the curves start to drift up.

To counter that, you can use the step cycle delay function.


Even with the step cycle delay activated at the maximum delay, the curves still drift upwards, a sign that it still gets hot quickly. Note the beginning of blossoming due to the difference in temperature with the triangle waveform going up, and then down. This is a very typical effect caused by thermal heat.

When you need to make longer measurements with these kind of power devices, it may be wise to add a heat sink to it and/or use a fan to keep it from a runaway-thermal effect that could damage or even destroy the device.

With a specification of 900V for the VDSS, we cannot do the Breakdown Voltage test with the maximum of 200V that is at our disposal.

 

More measurements will be added...

 

 



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