DIY Build of the Tek SG505 Oscillator

 

The rather famous SG505 oscillator

I'm going out on a limb here. Although I already built a copy of the SG502, described here, the SG505 is a very different beast all together. At the time I did the SG502, I was not ready to attempt the SG505, a masterpiece of analog engineering by wizard designer Bruce Hofer. After a number of years mulling about it, I was recently looking at the instrument again after seeing it used in a YouTube series, and this time decided to give it a try.

As with many, if not most Tektronix designs, they incorporate special parts, or the parts are obsolete by now. The added difficulty is that with these older designs (this one was created in 1980) that pre-date the internet, you can't find any datasheets for these parts. Most manufacturers went defunct or merged and do not show these old parts on their websites.

So when looking at the SG505, I first wanted to try to build the sine wave oscillator. I used the information from the Option 2, that has the balanced outputs, because that has improved schematics and parts.

Here is where you can find a lot of information about the SG505 and it's designer Bruce Hofer.

So what is so special about the SG505

First of all, among specialists, it has the status of a real piece of analog art, designed by one of the great masters himself, Bruce Hofer. While at Tektronix, Bruce was responsible for many products and designs in the 7000 oscilloscopes and the TM500/5000 series. He also designed the AA501, the first automatic audio analyzer that worked in tandem with the SG505. As a matter of fact, I understand they designed the AA501 to verify the SG505 after production. In the manual for the SG505, you can see the rather elaborate method to calculate the total harmonic distortion, and the equipment needed. 

Just the specification of 0.0003% THD from 20Hz to 20KHz will give you an idea of the design quality. 

The SG505 has at least one patent that I know of, describing a "State variable oscillator having improved rejection of leveler-induced distortion". Have a look here : patent.

When Tektronix management was not interested in taking the AA501 and later the AA5001 distortion analyzer concept further, Bruce co-founded Audio Precision and that is the current and undisputed leader of this field.

You may ask why I'm so interested in rebuilding the SG505? First of all, it's a great design made by one of the few analog wizards. It is very well documented and also has been manufactured for several years so the selection of components went through this test. This "fitness for manufacturing" should not be underestimated, because the parts (source, value, tolerance, tempco, etc) in every possible permutation will have to meet the specification of the final product over the years. In other words, the bugs are out. This cannot be said about many other DIY designs.

The other reason for selecting the SG505 is that you can freely select any frequency by just selecting the desired range, and using the dial and vernier adjustment to select the frequency you want. There are several other pure oscillator designs that are more modern, and even have better specifications. In almost all of their applications, they are used in a THD measurement, and in those cases, you "only" need a few fixed frequencies. That makes it easier to get better specifications because you can tune both sine and cosine oscillators with fixed parts. None of them use an analog variable frequency selection.

Some Small print:
As I normally do on my Blogs, I describe the way I get to the final design, with trials and errors, ups and downs, warts and all, but hopefully in a way that you learn something, and avoid my mistakes. With my projects, it's not going to be an IKEA hand-holding type design. Some effort is required. And most importantly, there are no guarantees it will work for you too, I'll do my utmost but that's about it.

I will add information to this Blog and the Github as I go, and with this pretty extensive project, it may take a long time. As a matter of fact, I may not be able to finish it with the sought after quality, so take that into account before you heat-up your soldering iron or start to order parts. I'm not a really experienced engineer, and I'm not hampered in any way with specific know-how or experience, nor do I have the proper equipment to verify and test the design. I'll do my best, and will make you part of the process, but that is as far as I can promise.

Interesting articles and information:

There are many articles about sine wave oscillators, because building a simple one is easy, but a really good one is a real challenge. Over the years I have collected a few interesting ones:

Rod Elliot has a lot of interesting information on his site, but there is one particular posting where he explains the various architectures with their pro's and con's.
https://sound-au.com/articles/sinewave.htm

A few other articles can be found on my Github site here:
https://github.com/paulvee/DIY-Rebuild-of-the-SG505.

Then there are several Forum posts that deal with the modernization and rebuild of the Bob Cordell THD Analyzer that contains a very good oscillator, just like the SG505 (that original article is on my Github). The latest and most impressive rebuild of that instrument that is 30 years old, but now with a processor to drive the measurements is on this Github from Emile666, a very impressive and complete design. Also have a look at the diyAudio site, there are designs that deal with specific 1KHz and 10KHz pure oscillators of outstanding specifications (search for "LT AN67 1KHz or 10KHz oscillator", from Frex) The AN67 application note is listed on my Github. The author of that impressive design is the rather flamboyant Dale Eagar, who worked for my buddy in crime Bud at LT. Small world.

Component Issues & Challenges

For this particular project, let's discuss the road-blocks and challenges for a rebuild, based on the components that are used in the instrument.

First off, there are several special parts and some of them are no longer available on the market.

The potentiometer that sets the frequency is a high quality single turn dual 10K wirewound version without a stop. It was originally made by Spectrol, but is now part of Vishay. The part used is a Model 100 with the following part number: 100B2-103-103-XXXX

According to the datasheet, it has +/- 3% tolerance and the independent linearity between the two sections is only +/- 0.5%. Unfortunately, the datasheet does not specify the THD. This part is still active and manufactured it seems, but nobody has it in stock. 

The next item is a mechanical part that is used in combination with the potentiometer, to create a finer adjustment by reducing the number of rotations 6:1. The Tek part number is 401-0161-00 and the manufacturer is Jackson Bros (London). Their part number is listed as 4511/DAF in the SG505 manual, and believe it or not, you can still buy this part for a reasonable price, here. This reduction unit also gives a very smooth and controlled action on the potmeter. Highly recommended!

I am the lucky owner of having the potmeter and the reduction unit, it is used in my SG502, but for others, I'm going to try to find a replacement part or method for it. It's the most critical part of the design so it would be critical to find an alternative. I have some ideas using other potmeters, even digital ones but I have no experience with them whatsoever so I need to give that a try when I have a functioning oscillator.

The next item in the list is the special drum switch (or cam shaft) that Tek manufactured themselves that select the output attenuation. This in addition to the special pushbuttons that are used to select the frequency multipliers. In my design for other Tek instruments, like my 5CT1 (below) where I added readout capabilities and also for the SG502, I used reed switches or a small relay in combination with a simple rotary switch and diode matrixes to re-create the sometimes rather complex switching arrangements. 

Luckily, the SG505 switching used is quite simple. At first I was contemplating using analog CMOS switches or MOSFET's, but I understand that will add too much resistance or add to the THD distortion budget, so I will most likely use reed switches again.

Next-up is the J-FET used in the AGC circuit. The Tek part number is 151-1021-00 and is used in many Tek products. In the manual, they show the FN815 from Siliconix. I have not been able to find any information about that part at all, and I know I'm in good company because of the frequent use in other products. Many makers are looking for replacements. There is another J-FET 151-1025-00, an SFB8129 made by TI that is also used in many designs. This J-FET is used in the power supply as a current source, but that one is a lot less critical. Lastly, that same J-FET is also used in the output buffer amplifier. 

One of the most critical components, in terms of the distortion budget, is the special hybrid substrate that is used to select the dBm output settings. I happen to know that the construction used in the SG502 is the source of some extra distortion, so Bruce Hofer created an unofficial modification to change that for the SG502, significantly reducing the total harmonics from an original 0.035% THD to well under 0.002%. My assumption is that using discrete components is going to be a challenge, but on the other hand, we now have very good SMT devices Bruce didn't have at the time.

Lastly in this list is the set of matched timing capacitors used in the oscillator phase-shift amplifiers. Luckily, for a DIY project, the absolute values that are matched in the SG505, are less critical. In a manufacturing process, you don't want to tune the product, it has to work right of the production line with as few adjustments as possible. The critical factor for the original design was to create a situation by which the frequency dial is set to say 1, and by selecting the X10, X100, X1K and X10K, you would would get the exact reading of 10Hz, 100Hz, 1KHz, 10KHz and 100KHz +/- a few percent, but we don't really care do we? Besides, we don't have the frequency dial anyway. We will need to work around that.

I already have a little and simple side-project working, using an Arduino Nano and a small OLED display to measure and show the frequency.

Simplifications for the DIY design

From the outset, I will be concentrating on the sine wave oscillator itself. I'm not planning to add the differential output that the Option 2 provides. What I will eventually use as the sync output is still open. All I want is a way to trigger my DSO on the signal, and an edge of a square wave is actually more stable to trigger on than the slope of a sine wave. 

I will also not implement the Intermodulation Module because I don't see the need for it in my projects.

Next up is a more simple instrument setup. The original SG505 has to function in a TM500 or TM5000 mainframe, together with a host of other instruments right next to it. Some of them can be very unruly and noisy neighbors. The SG505 is completely floating from real earth ground inside this environment. My plan is to keep it that way, but build it in an enclosure that has no earth ground connection anyway, so it will be floating from the outset.

The power supply is a critical element in the chain and will deserve a lot of attention, but I will address that later. I will use my lab dual power supply in the beginning.

My Plan

My plan is to build a prototype PCB that will give me a functioning oscillator that will allow me to test and try some different strategies and components, and build a reference platform for my measurements using my mostly home-brew set of inexpensive tools. Some if which I already have, some I may need to build to verify and test the specifications. I envision something similar as the design of the VBA Curve Tracer, where we went a step at a time over the course of about two years.

After going through the documentation many times, and watching YouTube videos and strolling the internet for information, I started by creating a schematic in KiCad. I then spent many long hours pouring over the Replaceable Electrical Parts list selecting and finding the parts for the prototype. I used Google, Mouser, DigiKey and LCSC for days, and eventually decided on a BOM to order from LCSC because of the total price including S&H. It turned out that they did not have one particular resistor value from all the parts I need, so I ordered a combination of two to get the missing part.

I did not save money on the parts but selected the best quality. All resistors are 1% metal film, better than the original THT resistor specifications. I also matched or exceeded the higher precision resistors (like 0.1% at 25ppm). However, I did not use Mica capacitors, but good quality NPO with the same 1 or 2%  tolerance. The electrolytes are all Tantalum except for the two used in the supply rails.

Almost in parallel, and now knowing the parts and footprints, I started to design a PCB and ordered it as well. Both the parts and the PCB's will be on their way soon. Talking about on their way, another "way", PCBWay has agreed again to sponsor me with this project, and I'm grateful to get boards from them for free and with a very high quality. I may need to go through a number of re-designs while progressing so this support is very helpful.

The schematic for the prototype

This is after I fixed the discovered errors.

The component names and values are the same as in the original schematic in the Option 2 manual. Where they do not, or I had to use other parts, I indicated that.

However, I deviated quite a bit from simply redrawing the original schematic in the manual, to show the many intricate and not-so-obvious feed-back and feed-forward connections, as well as the many compensation circuits, especially around the inverting Opamp U1510. This is where most of the magic happens.  I suggest you read the Theory of Operation in the manual and also the patent application for the feed-forward invention, that allowed Bruce to significantly reduce the harmonics. In essence, he applied his wizardry to remove the fundamental frequency AC signal from the AGC circuit DC-level in several places. I know that the picture above is not of great quality, but a Github project is available here and I will upload files as the project progresses.

The three hierarchical boxes in the schematic are "hiding" the frequency and dampening switches and parts but are inconsequential at this moment. I just followed the original design, but used jumpers instead of switches.

The 2-layer PCB prototype

The layout of the PCB largely follows the schematic, so there is a full circle with the circuits following the State Variable design as is in the schematic as well.

I made the decision, right or wrong, to use ground fills on both sides of the PCB. We'll see if that will show up as an issue, in which case I need to go to a "star" grounding method with all ground going to the output BNC connector.

For this prototype, I will be using jumpers to select, add and try components and also activate the capacitors for the frequency selection and the AGC damping. For the frequency selection, I will use a normal dual (stereo) cermet 20K potmeter, just to have a functioning oscillator. 

J-Fet Selection

I added two kind of foot prints for the J-FET so I can use SMD and TFT to experiment. The TFT version has a socket. I actually have the original but now elusive unobtanium J-FET, and I also have a Curve Tracer, described here, so I can verify or measure the specifications if needed. I already ordered or had a small selection of J-FET's to try.

The elusive, unspecified & unobtanium 151-1021-00 J-FET

While waiting for my parts, that were returned to sender because a very bright DHL delivery person could not find the apartment I lived in for 17 years, I started to look for alternatives for the 151-1021-00 JFET. I already had a number of candidates, and more are in the shipment so I could get started. As a spoiler alert, I think I have been successful, but I now need to test the alternative 2N4391 in the real circuit, and compare the results with the original 151-1021-00 part.

Because I did not do a write-up for testing JFET's with our Curve Tracer yet, I added that episode to the following document. Scroll down to the end in that posting to see the JFET result.

Making measurements with the VBA Curve Tracer

Capacitor Selection

For the frequency setting capacitors, I used good quality Polypropylene film capacitors, but now that modern NPO and COG ceramic capacitors are available in good quality and with very precise tolerances, I may want to experiment with them as well. I will most likely trim the Polypropylene values to match by using the ceramic parts, and measure the effects.

What are the chances of success for the rebuild?

I'm very anxious to see what the results of this prototype is going to be. When I built the SG502, I was pleasantly surprised that my rats-nest construction (no PCB) produced a slightly better THD specification than the production version one had. A testament to the conservative specs and the quality of the original design. 

Who knows what I find with this one...

How am I going to verify the results?

As I stated earlier, I do not possess all the proper equipment that is required to really verify the SG505.

I will have to do with less and see how far I can get. If needed and possible, I can build something, like the passive notch filter (067-0938-00) that the Tek engineers designed specifically to test the SG505 performance. 

I already have an active T-notch filter for 1KHz that I may need to duplicate or extend for the other frequency ranges (10Hz, 100Hz, 10KHz and 100KHz), we'll see about that when we get there.

Luckily, I have a kind-off reference oscillator, the Viktor Mickevich 1KHz design that has a very respectable THD. He claims (verified by others), a whopping <0.00001% THD. 

With my simple DIY equipment, (look at this post and this one) I could measure the THD for his oscillator as far down as 0.00096%, so that is a very good start.

For the rest, time will tell.

Possible solutions as an alternative to the dual 10K potmeter

As I mentioned earlier above, this frequency adjustment potmeter is a very critical part that is crucial for the operation and more importantly, the specification of the oscillator. The specification needs to be tight because of the "State variable" design of the oscillator. Each section of the pot sets the frequency for the two 90 degree phase shift circuits (states). If there is a difference in the resistance between the two potmeter sections, it will negatively impact the phase shift. The timing capacitors also have an equally important role, but they can be more easily matched to each other or the value tuned by adding parallel capacitors.

The combination of the original 1-turn 360 degree 10K potmeter together with the 4511/DAF 6:1 reduction allows the sensitivity or rather resolution to be as follows. For the potmeter, 10K / 360 degrees is 27.7Ohm per degree of rotation, further reduced by 6 to 4.6 Ohm per degree of rotation. And then there is the vernier adjustment of +/- 1% of the frequency. 

Looking at it from a frequency perspective, with the frequency multiplier at 1K, the potmeter can adjust the frequency from just below 1KHz to just over 10KHz. That translates to 1,000 Ohm for every 1,000 Hz, or 1 Ohm per Hz. 1 degree of rotation is 4.6 Ohm and therefore 4.6 Hz. The vernier range is 1% of the frequency so that translates to 10Hz at 1KHz and 100Hz at 10KHz. That will be not so easy to duplicate.

So, provided you can't get your hands on the original Model 100 potmeter, what are the possible options or alternatives?

After quite some time looking at alternatives, I came up with a few potentials.

1. Use a dual (stereo) cermet potmeter
With the right 6mm shaft diameter, it can also be used in combination with the 4511/DAF 1:6 mechanical reduction. The challenge is that these potmeters do not have very tight specifications. A good quality one will still cost about 25 Euro's and at best has a 10% specification, but I could not find a specification for the linearity between the two halves, and that is the more critical specification. An overall value miss can be adjusted with resistors at the beginning or end, but not in-between. This type potmeter is what I'm going to use with the prototype. I can use a trimmer to make sure both halves have the same value at a particular setting.

2. Use a dual 10 turn precision potmeter
This will give you a much higher resolution in setting the frequency, and you don't need the 4511/DAF reduction. The vernier circuit can stay as it is. The specifications for tolerance (3%) and linearity are better than for a cermet potmeter, but there is a significant price differential. A suitable one will cost about 46 Euro's. The downside is that you need to turn the knob a lot (10x) to go from the beginning of a range to the end. Even with this quirk it could still be the most viable solution. I searched at Mouser for candidates, and by the time you have made the criteria selection, there are only 4 left, ranging in price from 46 all the way up to 157 Euro's. 

The least expensive one is the Bourns model 3549S-2AA-103/103A

It has a linearity specification of 0.2%, an overall 3% tolerance and 50ppm/C. This is pretty close to the original Model 100 that has 0.5%, 3% and 20ppm/C.

3. Use a digital potmeter.
I have no experience with using them, but I first thought this could be the solution. So after reading a lot about these devices, I found that there are actually a few stumbling blocks for this particular application. With most devices, the voltage range of the potmeter is limited to 0..5V. The regular maximum granularity is 256 steps (there is a special one with 1024 steps). This means that from a 10K value, every step will be 39 Ohm. That's 8.4 times more than the original resolution, so the vernier adjustment has to be modified to cover the difference. That can be done, but digital pots have other issues, like the linearity and tolerance, and then there are the resistance of the wiper and, a bit less important, the end and beginning resistance. When you change from one setting to the next, there could be a jump or glitch in the frequency, although there are ways (zero crossing) to avoid or suppress that. On top of that they are not that good with temperature changes. 

Based on our particular circuit, one of the best solutions could be the TI PGA2310 designed for hi-end audio stereo volume control. It has excellent specifications, even removing some of the issues with other digital pots. The chip is not cheap however, with a price of  about 28 Euro's.

Most importantly, these digital pots will need some form of digital logic to drive them. Normally, you would use a rotary encoder as the input, and use logic or a processor to drive the electronic potmeter settings. I have not discounted this solution, it provides some potential but it's not my favorite to develop at the moment.

4. Use a rotary switch.
When using a rotary switch, you need one with a double deck and one pole per deck with at least 10 positions, so you can create 10 segments of 1KOhm each by using fixed resistors. By using tight specifications for the resistors, you can really get the best linearity and matching between the two sections and probably also get the best Tempco results, surpassing the original design. The downside is that you can't smoothly turn through the whole frequency range, you have to select a section (1/10th of the range) and than use the modified vernier (modified to 10x the adjustment) for a finer resolution within the section. You can select shorting and non-shorting versions for these switches to avoid large frequency jumps when you switch. 

The suitable devices I found will set you back by about 45 Euro's. This is a rather complicated solution for a rather cumbersome user experience, so not my favorite to develop. For almost the same 45 Euro's, you could also buy the dual 10K Bourns.

Summary:

Depending on your particular application for the oscillator, there are a few options you can select from.

Frequency Display

As mentioned above, because we don't have, or will have a dial, I'm planning to use a small OLED display to show the frequency of the SG505.

Here is the prototype with an Arduino Nano and the tiny display I'm planning to use. I like the yellow color. The dimensions are 0.9" with 128x32 pixels.  I tested the FreqCount library from Paul Stoffregen with my function generator, and it easily covers the range of 10Hz to 200KHz.

The boards arrived.

I received the boards from PCBWay within a week of posting the Gerber files. They are really fast.

There is no gold plating, that is the light fixture playing tricks. The quality of the boards is great, as I came to expect from PCBWay. They also sponsor me for this project which is highly appreciated!

Update on the parts ordering saga:

Unfortunately, the parts I ordered at LCSC are still in limbo. They have been returned by DHL to the European distribution center and will then be sent out again. Hopefully this time DHL selects a more intelligent driver that can find the apartment I have lived in for 17 years. In his ultimate wisdom, he determined that I don't live here, and instructed to have the shipment returned to sender. DHL was unable to reverse this mindless decision. Great! The order was placed on March 4 and I'm told it may take another 1-2 weeks before I can get my hands on them. I just received notice (April 2nd) that the parcel has been re-discovered and this time I instructed DHL to deliver it at a pick-up point so I can pick it up tomorrow. Finally.

Well, on April 3rd, I finally have the parts in my hands and can continue with the project.

To create the best possible frequency selection, I selected the best matching capacitors for the timing ones. Because my minimum ordering quantity was 5 for the 1uF and 20 for the 100nF, 10nF and 1nF all with 5% tolerance, I could easily get matching pairs, but not precise values. That can be tweaked later if needed, but I don't think I need that. The matching between the values is much more critical for the distortion budget.

I also should mention that I'm using the Tektronix 151-1021-00 JFET in the AGC circuit. I'll investigate alternatives later.

First power-up and test

I used my new hotplate reflow solder station to solder all the SMD parts, and that went very well. I then added all the THT parts, and after thoroughly soaking and cleaning the board twice and inspection with a microscope, I tested the power rails for shorts. No issues, so I then used my Lab supply to provide +/17V at 50mA each and gave it a go. My DSO was showing a nice sinewave! Great!

While going through the range selection with the jumpers, I noticed that I goofed with the schematic and subsequent layout for the 10K multiplier selection jumper J15. A few trace cuts and jumper leads fixed that. I also noticed that turning the frequency potmeter didn't really change the frequency. That was caused by me flipping the 3-pin connector the other way around for one half of the potmeter on the PCB. Swapping the connector leads also fixed that. I now had a fully functional sine wave oscillator.

Frequency selection

Because I use a "kind of" dual 10K potmeter (see above), but with separate adjustments for either half, my plan was to see the effect of "in-equality" of the two pots, and adjust them to be exactly the same by using an ohm meter. The goal was to see what effect the in-equality (not only the linearity) would be on the distortion. I will get to that later. However, because of my goof with the connector swap, I stumbled on an optical verification of the in-equality or tracking. When you swap the connector, so one half of the pot will drive one phase change circuit with an increasing value, and the other phase change circuit with an "equal" decreasing value, the frequency should stay at the same value. But only if the two pot halves track each other 100%. Mine does not, there are slight changes in the frequency when I turn both pots together. 

Here is what I'm seeing. At fully CW or fully CCW, the frequency is almost the same at say 308Hz. During the rotation of the potmeters together, I see the frequency dipping down to a minimum frequency of 259Hz somewhere at 75% of rotation and then rather rapidly going up to 308Hz again. My calculator shows that to be an error of a whopping 19% in frequency which is quite a lot. 

To put that in perspective, the 10K potvalue creates a frequency range between 83 and 1.100Hz, or 1.017Hz. That means 9.83 Ohm/Hz, so a tracking error of 308-259=49Hz/9.86Ohm=5.96% of 10K. That's more reasonable, but it shows how important the tracking specification is. And we don't even know yet what the distortion contribution of this tracking error is.

I will do that same measurement with my original Model 100 precision potmeter later.

Does it meet spec.?

I use my dual lab supply to supply +/17.00V. The current consumption is 24mA for the positive rail and 26mA for the negative rail.

The sine wave output is 2.04VRMS (6.00Vp-p) into 1MOhm , and that is according to the specification.

The frequency ranges are within specifications.

• 10x     8Hz to 111Hz
• 100x   83Hz to 1.1KHz
• 1Kx    833Hz to 11.7KHz
• 10Kx  8.8KHz to 107KHz

When I go beyond 107 KHz, the sine wave collapses, so that's really the maximum.

The Vernier adjustment at a frequency of 10KHz goes from 9.92 to 10.12KHz, also good enough.

The AGC circuit works well, visually, but I did not test that any further.

When I set the frequency in the 10x multiplier setting, and adjust the frequency to mid-range and then select the other multiplier settings I see this:

• 10x     50Hz
• 100x   515Hz
• 1Kx    5.26KHz
• 10Kx  55.2KHz

This to me a fine, but can be further tweaked by using trimmer capacitors.

So what is the distortion?

I had some issues to find and load the drivers for my modified Creative EMU-0202 USB "Sound Card" (look at this post for more information), after I went to a new Laptop a while ago after a major W10 induced debacle. Most of the installed software had to be installed again, but I didn't need the FFT capabilities until now.

After some experimentation, here are the results with the PCB just lying on my desk. This is with the range setting at  x100 (100-1000Hz), and using jumpers instead of the frequency select potmeter, to eliminate the leads and the potmeter tracking differences. That puts the frequency at the top of the range at about 1.1KHz. I'm using a DIY 600 Ohm -10dB attenuator, and the E-MU0202 and the ARTA software is calibrated with it. Note that this is taken straight from the oscillator output, and not from a "real" output amplifier. I do not yet know what impact the 600 Ohm loading is for the circuit.

Not a bad result I think, but not near the specification of <0.0008% in the 20Hz-20KHz range.

After several hours trying, searching, testing and pulling some valuable hair, I now know why these results are too far away from the original specification. First of all the settings in the ARTA software.

Second, the 600 Ohm -10dB pi attenuator I was using to feed the E-MU with a lower input signal is indeed loading the oscillator circuit and is the cause for the higher THD distortion. Rather than showing all the previous results I made, I'm now reverting to the setup with the 100K loading of a potmeter at the output of the oscillator circuit so I can reduce the signal amplitude. 

This is the result:

The specification is <0.0008% THD so we're significantly below that figure now.

As a reference, I also made a measurement using the Victor Mickevich oscillator, and that shows this:

It seems my measurement setup is OK, apart from the larger amount of noise. Earlier measurements from a few years ago using the same modified E-MU0202 and oscillator, but with older versions of the software and drivers and a different laptop, produced seemingly better results so something is a little different.

I also tried my Arduino frequency counter, and although it works fine, just taking the input through a capacitor from the circuit output produces a lot of harmonics, so it needs a separate buffer amplifier. The oscillator prototype itself also needs a buffer amplifier, so I'm going to add that and see how the counter behaves then.

Here is a measurement using the potmeter to adjust the frequency to a precise 1KHz.

Apart from a little bit more noise (six long leads to the potmeter) there is no difference to the THD, so I'll continue with the potmeter installed from now on, and revisit the possible effect on the THD by the tracking tolerance later.

Output amplifier circuit

Because of the loading on the circuit by as little as a scope probe (added noise) and the sensitivity to loading the circuit with an output impedance (adding harmonics), I quickly put together an output amplifier circuit. In hindsight, I should have added that to the prototype, but I didn't...

I am now using the Arduino based counter to show the frequency so I don't need to use my DMM or DSO anymore, reducing the amount of loading and adding noise. With the potmeter at the output, I can now set the voltage level for the E-MU 0202 so it does not show harmonics. The input voltage to the E-MU needs to be around 1Vrms to have the least amount of distortion.

Distortion and the supply rails

Form what I can gather, there is no need to have tracking supply rails with a high accuracy. I could reduce the positive supply by 1V without  a change in the THD. However, the circuit is more critical to the negative supply. If I lower that by 1V, the is a 0.002% change in the THD+N. Lowering both rails to +/- 15V has an even larger effect. I initially thought that the increase of the rails from 15 to 17V was due to the Option2 output amplifier, but I now think that they raised the rails to get a little better THD result.

Power Supply

I've finished a simple textbook separate mains fed power supply for the prototype that has the +/- 17V rails and also the +5V for the counter, and later the relay/reed switch section.

I'm using a toroid transformer that has two separate 24VAC windings.

To get the +/- 17V rails, I'm using the LM317/377 adjustable voltage regulators, and added a trimmer to adjust them. The 5V rail is tapped from the transformer in a way to reduce the loading or digital influence. That voltage is too high for a normal LM7805, so I'm using another LM317 that can have input voltages up to 60V to get the 5V. 

The grounding for this prototype is simple. Later on I will probably split the two windings and create separate supplies for the +17V and -17V, and use a star ground at the output connector for the analog circuits. The digital circuits (the Arduino Nano and the relays/reed switches) will be kept on the 5V rail and that GND will be as separate as possible.

Running an FFT of the +17V rail with a DC blocker shows that there is a bit more work to be done:

The 50Hz mains comes through, and there is coupling back to the rails from the (1KHz) frequency of the generator.

Granted, it's all just lying on my desk without any shielding from my other equipment (10MHz master clock, and 2 x 10MHz GPSDO) or the quite noisy environment (switching power supplies, DSO, DMM, WiFi transmitter).

After some thinking about the power supply, I decided to make a detour and give the SG505 a more worthy supply. This quick-and-dirty-put-together supply was a failure, so I ripped it apart. 

I have been aware for years of the so called "Superreg" design from Walt Jung from a few decades ago. He designed it predominantly for audio projects, but hey, if it's good enough for critical hi-end audio applications, it should also be adequate for the SG505. At least that is my current thinking.

I don't want to add that project to this blog post, so I'll start a new dedicated one. Superreg

Distortion and the potmeter tracking

This effect turned out to be more difficult to measure than I anticipated due to the significantly changing THD numbers that are reported by the ARTA software. Changing the value of one of the potmeter halves is more difficult that I anticipated, due to the minute rotation change and the large change in frequency.  To get a better visual handle on this, I used my DSO in the X-Y mode and use the two input channels to look at the output of the two 90 degree phase shift Opamps. It should produce a circle, which it does, but you can't really see enough of a change relative to the changing distortion numbers. In my opinion, it is safe to say that the closer the specification for the tracking is, the better the distortion numbers will be. The overall tolerance of the 10K potmeter value is less important. If needed you could add small resistor values at the bottom and/or top of the potmeters to create equal minimum and maximum values without disturbing the tracking.

Distortion and the JFET selection

That will be next on my list.

My current test bench

Stay tuned, there will be a lot more to come now that I have a functioning prototype...

A Github repository is available here it will be updated with information during the project.

Making Measurements with the VBA Curve Tracer

This post will describe a number of measurements that can be made with the VBA Curve Tracer, described in another post. More measurements will be added or maybe changed so keep an eye out for additions and changes.

The building of the first version, actually a working prototype, with a detailed Theory of Operation.
https://www.paulvdiyblogs.net/2017/

There is also a description of the second generation based on the first prototype. This is a fully functional CT but has some problems and shortcomings that we're addressing in V3.
https://www.paulvdiyblogs.net/2021/03/building-curve-tracer-v2.html

The design process of the VBA Curve Tracer.
https://www.paulvdiyblogs.net/2021/03/building-curve-tracer-version-3.html

Reference Documents

I will try to follow a number of documents as the guideline for testing since several of you will have some experience with the Tektronix 577 & 576 workhorses. These instruments are still used in many workshops, labs and classrooms so chances are you have used them. Unfortunately, these instruments are dying of old age and cannot be fixed anymore mostly due to unavailable replacement parts. 

We cannot do all measurements these benchmark instruments can make with our CT, but we can do many.

There are a number of documents that I used as guidelines for these measurements. They are listed here:

Tektronix 577 Device Testing Techniques:
https://w140.com/Tektronix_577_DeviceTestingTechniques.pdf

Understanding Power Transistors Breakdown Parameters
https://www.onsemi.com/pub/Collateral/AN1628-D.PDF

Bipolar Transistors, Terms used in data sheets:
https://toshiba.semicon-storage.com/info/docget.jsp?did=63511&prodName=2SA1225 

Specifically for Section 7:
Depletion MOSFET's or J-FET's
https://aldinc.com/pdf/IntroDepletionModeMOSFET.pdf

https://www.tek.com/en/support/faqs/how-do-i-test-jfet-small-signal-forward-transfer-admittance-my-curve-tracer

Making measurements

WARNING:

Before making any measurements, make sure you are limiting the current to the DUT when powering them. It is very easy to damage them or even blow them up if you are not careful. This is especially true for MOSFET's due to their low RDSON. 

Optimum DSO display settings:

If you are going to make screenshots of the DSO display, you need to probably change two settings to get the most optimum pictures. The first setting will reduce the fuzziness of the traces, which is the number of samples. With my Rigol DS2302A, I need to go to the Acquire mode and select the Memory Depth to be 7KPoints. The get a brighter trace, I set the WaveIntensity in the Display mode from 50% to 100%.

So with the finished VBA Curve Tracer instrument, and with some of the inherent limitations of a DIY instrument, what measurements can we actually do? Quite a few actually...

1. A few generic measurements

Setup to profile a small signal BJT

Let's look at the venerable 2N3904, probably the most popular small signal NPN BJT. This is a 40V VCEO transistor that can handle an IC of 200mA and has an hFE (beta) between 40 minimum (at 100uA IB and VCE of 1V) and typical 300 (at 1mA IB and VCE of 1V), which is a very large spread. I suggest you look at the datasheet for reference.

2N3904 Data Sheet

 

So how do we use the Curve Traces to look at this device? 

For reference, look at the Face plate above. I'll do the setup going from left to right. 

But first, turn the Sweep Voltage to 0% and set the DUT selector to the off position. 

It's good practice to do this before every start of a new setup or measurement. It's a good way to prevent DUT losses.

Step Delay should be off. Offset should be off. Select the N Polarity.

Select the BJT mode and select 7 steps. Set the Step Base current output to 50uA/step.

 

Set the Current Limit to 0% (no output, CL indicator should be on). 

Set the current range to x0.05 to create a maximum current of 2A x 0.05 = 100mA. 

Set the X-Amp to x10, this is for small signal devices. Higher powered devices will need the x1 setting.

Set the Voltage Range to 35V.

 

On the DSO, select the X-Y Time base. 

Adjust the sampling mode of the DSO to a lower setting, I use 70KPoints to reduce the noise.

Set CH1 to a Ratio of 10x so the readout is 1:1 with the Sweep Voltage. Select a limited bandwidth to reduce noise. I use the lowest setting of my DSO; 20MHz. Set the input to 10V/Div.

Set CH2 to 10mV/Div, 20MHz bandwidth and a Ratio of 0.1x to make the readout 1:1, meaning that 1mV represents 1mA.

To get a feel for what the relationships are in Volts/Division in relation to the DUT Collector Volts and Amperes we're going to measure, I recommend you to first use a 1K resistor in one of the DUT sockets between C-E.

 

Adjust the vertical positions so the dot is at the cross-hairs of the first division vertical, and the first division horizontal (the 0V and 0A origin). This is the I/V origin.

Turn the voltage adjustment so you have a line starting from the origin that will go 3 division to the right.

You should have the following display on your DSO:

CH1, the horizontal Y-channel: We use 10V/Div, with a Ratio of 10x. This will show the Collector voltages at a 1:1 ratio so 3 division horizontally is 30V (VCE).

 

CH2, the vertical X-channel: We use 10mV/Div, with a Ratio of 0.1x (the ratio of 0.01X you see on the right hand side menu is incorrect) , which results in a display of 10mV/Div representing 10mA/Div. of Collector current (IC). 

 

We use a 1K resistor, and applied 30V across it, resulting in 30mA Collector current. This is represented by 3 divisions vertical deflection of 10mV/Div, or 30mV and that equates to 30mA Collector current. 

In case your DSO does not support the Ratio factor, you need to memorize what it shows and always work out the conversion for the Collector current.

Reduce the Voltage and Current adjustments to 0% and remove the 1K resistor.

Set CH1 to 2V/div and CH2 to 20mV/Div.

Plug a 2N3904 transistor in the right DUT socket.

Select the right DUT position to apply power to the transistor. Turn up the Current to 100%, the CL indicator should be off. Turn up the Sweep Voltage to have 5 divisions horizontally, which will be a Collector voltage of 10V.

You should now have the following display or close to it:

 

 

So what do we see here, apart from the wrong ratio (0.01X should be 0.1X)?

The first step of the cycle is with a Base current (IB) at 50uA, the second at 100uA, the third at 150uA, and so on. We see that the first step shows about 10mV. The 10mV represents a Collector current (IC) of 10mA so the hFE or beta (IC/IB) will be about 10mA/50uA or 200. You could do this calculation for every step or at every IB.

We can see that the beta at the others steps does not change much with higher Base currents and also with different VCE's at these higher IB's. The gradual changing of the flat lines into a slope is caused by the Early Effect (https://en.wikipedia.org/wiki/Early_effect).

So what happens when we lower the Base current?

When we lower the Base current to 10uA/Step, and set the V/Div to 2mV, we get the following result:

 

 

Note that the distribution per step is now much a bit  more uniform and the lines stay more horizontal. This is a much better operating area for this transistor.

We can go even lower, to 1uA/step:

 

With the current setup, with the Face plate/Front board sandwich and the long wires to make it all work, together with the DSO at 100uV/Div, we have quite a bit of noise.

When we raise the Base current to 200uA/step, we are bumping into the maximum Collector current area of 100mA. Note that the Collector current is now cut-off at about 80mV or 80mA.

Luckily, we set the maximum current to a limit of 100mA, because without it, we could have killed the transistor due to thermal stress. If you use your fingers on the device, you will notice that it will get warm, but with this current limitation, there is no harm done to it.

 

We can measure the device with a higher current limit, but in order to reduce the thermal stress, we need to activate the Step Cycle Delay function, and set that to about the maximum. You can probably adjust the delay to a point where the display does not flash anymore.

Now we can select a higher current range by changing the range from 0.5x to 0.1x, which at a maximum current of 2A will now be 200mA which is the limit of the 2N3904.  

 

The transistor is conducting a maximum Collector current of about 130mA and could easily go beyond, but it is Current Limited, and therefore does not get overly hot. The display does not drift upwards due to the thermal stress that increases the beta, which is a sure sign that the device is getting into a thermal run-away that could lead to its quick heat-stroke death.

Measuring the maximum Collector voltage

 

This is not the "official" method but shows a quick-and-dirty way. The 2N3904 is specified with a maximum VCE0 of 40V, lets see what happens when we raise the voltage. We set the Base current back to 10uA/Step, set the Voltage to 0%  and switch to the 75V range. Select the X0.5 Current range and set the Current to 70%. Slowly raise the Sweep voltage to about 55V.

 

Beyond 40V, the transistor is getting near the breakdown voltage (VCBEO) and the Collector current begins to skyrocket due to the avalanche effect. This is a measurement you should make very carefully. The VCBEO specification for this transistor of 40V is met. 

Note

Because the Collector current goes up fast due to the avalanche effect (breakdown and potentially even punch through), setting the proper current range and setting the current limiter is very important because the device can easily get damaged or even destroyed before you know it.

 

Below is a properly protected device using the Step delay and current limiting.

  

Profiling a diode

 

I'm using the well known 1N4148 diode as an example. The diode gets connected between the E and C connections in the ZIF socket. Connect the Anode to C and the cathode to E. We set the current range to x.05 and the CL at 25%. Start with the 35V range for the forward voltage. Set the Sweep voltage to 0%.

Set the DSO hor. channel to 200mV/Div and the vert. channel to 1mV/div.

Set the polarity to N.

Slowly turn up the sweep voltage until current starts to flow.

The voltage when the device starts to conduct can be seen here and is at about 500mV and goes up to about 750mV with a higher current. The diode has specifications for different forward voltages at various currents. The specification says between 0.62V and 0.72V at 5mA. That is what we see here as well.

Reduce the sweep voltage and select the 200V range. Set the hor. channel on the DSO to 50V/Div Change the polarity to P to reverse the voltage to the diode. Slowly turn up the sweep voltage until there is current flowing again, signalling the maximum reverse voltage. 

The reverse voltage is about 180V, the specification says 100V. Check!

Profiling a Zener diode

 

I'm using a generic 10V 1/4W Zener diode. Set the voltage range back to 35V, and set the hor. DSO channel to 200mV/Div. Select the N polarity and connect the Zener diode with the Anode to C and the Cathode to E. Set the current range to x.05 and the CL at 25%. Set the sweep voltage to 0%.

Select the DUT socket and slowly turn up the sweep voltage until current starts to flow.

The forward voltage is about 680mV at 6mA.

Reduce the sweep voltage and switch the polarity to P to reverse the voltage.

Slowly increase the sweep voltage until current starts to flow.

The Zener voltage, or reverse voltage is exactly 10V at 1mA but increases slightly to 10.1V at 7mA.

Further measurements can be made by increasing the current and see what the Zener voltage does.

Set the vert. channel to 20mV/div. and slowly increase the current by adjusting the CL.

At 100mA, the Zener voltage is now at least 10.2V, something to keep in mind when you design circuits.

 

Profiling a Schottky diode

I'm using the popular 1N5819 Schottky diode.

 As to be expected with a Schottky diode, the forward voltage is about 350mV at 40mA.

 

 

 

The reverse voltage is limited to about 54V. 

 

Profiling LED's

I'm using a selection of 3mm LED's with different colors to see what the difference in forward voltages is for the different colors, and also what the brightness levels are with the same current.

This is a white LED, the forward voltage is 3.4V at 40mA and it is by far the brightest of all.

This is a red LED and the forward voltage is 2.2V at 40mA, and it is very bright.

This is a blue LED with a forward voltage of 3.4V at 40mA, it is very bright.

This is a green LED with a forward voltage of 2.2V at 40mA, it is the least bright of all. Note that this has a small amount of forward voltage change per current, which is why the green, red and also the yellow LED's can be used in simple constant current circuits.

This is a yellow LED with a forward voltage of 2.3V at 40mA, it is also very bright.

 

Testing a capacitor for leakage

This is a new test after we added the DC mode for the supply.

In the following test I'm using two 1,000uF/100V 85 degrees C capacitors in series at allow the testing at 200V. These capacitors were actually used in my first prototype, and are probably not of the best quality. The manufacturer is REC.

At about 150V, the leakage current starts to go up and reaches about 4.2mA at 180V.

I also tested a 1uF/450V film capacitor. It showed the following results.

 

 

No vertical deflection, so no leakage. We do not show a "dot" because there is some noise on the signal.

2. Device Testing Techniques on a Tektronix CT as a reference

 

I'm using a number of measurements described in the Tektronix 577 Device Testing Techniques Handbook, available here:

Tektronix_577_DeviceTestingTechniques.pdf (w140.com) 

I'm using this information as my guideline, just to see if and how we can do the same tests with our CT.

Testing a BJT transistor

Test 1: Measuring the Collector-Emitter breakdown voltage V(BR)CEO

This is actually the preferred method to measure the C-E breakdown voltage as it is referenced in the textbooks.

 

The Emitter and Collector are in the DUT socket while the Base is left floating (not connected or open - this is the O in CEO). The Sweep Voltage can be in the 75V or 200V range, with the current range at x0.02 and the CL adjustment at 30%. The X-amp is set at X10 to have more sensitivity, and the DSO vert. channel is set to a 0.1 multiplier ratio to keep the readout in mV compatible to the IC current in mA. Start with a minimal Sweep voltage. Select the DUT and slowly raise the Sweep voltage until the current shoots-up rapidly and the voltage no longer increases. You can raise the CL limit a bit if it turns on to get a better picture.

In this case, the breakdown VCEO is at about 60V, while the specification is for 40V. Note that the current is about 80mA.

 

One side effect from this breakdown event is that it also trips the Step protection causing the Fault indicator to come on, even though the Base of the devices is not even connected. This is caused by the violent breakdown event that turns on the sensitive protection circuit which removes the Collector output for about 16mS, after which it is released again. This is an extra protection for the DUT as well because it limits the dissipation and the amount of current.

Test 2: Measuring the Emitter-Base reverse breakdown voltage (V(BR)EBO

 

In this test, we will connect the Base of the transistor to the Emitter socket (grounded Base) and connect the Emitter of the transistor to the Collector socket. Leave the Collector lead of the transistor floating (not connected).

Set the voltage range to 35V and set the current range to x.02, set the CL adjustment to 40% and the Sweep voltage to minimum.

Slowly increase the Sweep voltage until the current shoots up which shows the breakdown voltage.

The V(BR)EBO is at about 7.8V, while the specifications is listed at 6.0V so the device passes this test.

Test 3 : Collector Cutoff Current ICEV or ICEX

Collector cutoff current is the IC that still flows when the specified VC and a specified reverse bias is applied.  It is normally less than either ICEO or ICER (collector current with the base open, or with the base resistively connected to the emitter).  This is because the reverse bias removes most thermal and avalanche carriers from the base.

Because of non-linearities and the effect of base drive source impedance, base drive is often specified as a current instead of a voltage.  The symbol ICEX is commonly used for the current method, while ICEV is used for the voltage method.  The current and voltage drive capabilities of the curve tracer permit either method to be used.

According to the data sheet for the 2N3904, the specification for ICEX is a maximum of 50nA at a VCE of 30VDC and a VBE of 3VDC. 

 

We can set the measurement up as follows:

Set the voltage range to 35V, and initially set the Voltage adjustment to 0%.

Set the Sweep/DC selection to output DC, Set the Current range to X.1 and the Current adjustment to 40% (about 80mA).

Set the BJT/FET selection to BJT. Set the Step Output to 10uA/Step. Set the number of steps to zero.

Set the offset to Positive and the adjustment to minimum.

Set CH1 of the DSO to 5V/Div, and CH2 to 50uV/Div. The X-Amp should be set to X10 and the CH2 Ratio should be 0.1 for that setting.

Select the DUT and slowly turn up the offset to move the dot to the first graticule line, indicating 50uA.

 

Increase the Voltage adjustment until you have reached 30VDC.

The reading of CH2 should be no more than 50nA.

 

 

Test 4 : Collector-Base Breakdown Voltage V(BR)CBO

 

With this test we measure the point when excessive current begins to flow between the Collector and the Base with the Emitter terminal open. The Collector of the transistor is connected to the Collector connection on the ZIF socket, The Emitter is not connected and the Base of the transistor is connected to the Emitter socket of the ZIF (grounded Base). The Sweep voltage range is 200V and the current range x0.2. CL at 80% and the Sweep voltage at minimum.

Slowly increase the sweep voltage until a Collector current starts to flow. You can adjust the CL to a better display.

The V(BR)CBO is measured at 90V, while the specification is at 60V.

Test 5 : DC Forward Current-Gain (DC Beta or hFE)

 

The DC forward gain is the ratio of the DC Collector current to the DC Base current.

We cannot really follow the measurement as described in the handbook because don't have an offset multiplier function. We have an offset, but it is not calibrated and cannot function as a step setting multiplier. The reason is that I decided against using a 10-turn potmeter with a scale for the offset. Adding an offset multiplier function would add more complexity to the circuit, too much to the price, and take up too much room on the Front Panel.

 

We can still do the measurements, but we will have to use a slightly different approach.

For the 2N3904, the hFE or DC Current Gain with a VCE of 1V is:

• IC = 0.1 mA, hFE is 40 min.
• IC = 1.0 mA, hFE is 70 min. 
• IC = 10 mA,  hFE is 100 min. 300 max.
• IC = 50 mA,  hFE is 60 min.
• IC = 100 mA, hFE is 30 min.
  

You would normally only do one measurement that is close to the intended application, and I will do the hFE for and IC of 0.1mA.

 

Set the CT Voltage range to 35V, Sweep. Set the Current range to x.05 and the Current adjust to 80%.

Select 0 steps. Select the Positive Offset and the adjustment to Minimum. 

 

Select the Step output relative to the IC specification. For an IC of 0.1mA and an expected hFE of 40, select 0.1mA/40 is 2.5uA, so select 2uA/Step to get close.

On the DSO, set CH1 to 200mV/Div and CH2 to about 1/6th of the selected IC of 0.1mA. In this case 20uV/Div. which represents 20uA/Div.

 

Adjust the Voltage very carefully so you have close to 1V on the DSO.

Adjust the Offset so the bottom line crosses the 5th graticule, meaning an IC current of 5 x 20uA or 100uA/0.1mA.

 

Now we need to measure and calculate the offset factor, because we do not have a calibrated one.

Use a DMM connected between the B-E DUT terminals.  Note the voltage that we just set. In my case it was 0.593V. Now turn the offset adjustment to full scale and measure the offset again. In my case I measured 0.675V. To calculate the factor, divide the maximum voltage by the adjusted value (0.675/0.593 = 1.138)

To calculate the DC forward current gain hFE:  5 x 20uA / 1.138 x 2uA = 100uA / 2.276uA = 43.9

Test 6 : Collector-Emitter Saturation Voltage VCE(SAT)

 

The VCE saturation voltage is the value of the Collector voltage below which an increase in specified Base current cannot cause an increase in Collector current anymore.

The VCE(SAT) is specified at 200mV with an IC of 10mA and an IB of 1mA. 

It is also specified as 300mV with an IC of 50mA and an IB of 5mA. 

We set the number of steps to zero, 1mA/step, 35V range, Volt at 0%, current range x0.1, Current at 80%. Step Delay on and at maximum to protect the transistor from over-heating. Offset positive and initially at minimum. Sweep voltage at 2.5-3V. On the DSO, set CH1 to 200mV/Div, and CH2 to 5mV/div. ( 5mA)

The following display should be the beginning situation:

 

 

Slowly increase the offset until the horizontal line, the IC current level, crosses the second graticule, representing 10mA.

 

 

 

The point where the vertical line transfers into a horizontal line is the VBE(sat) point. This is the point where no further increase of the Base offset voltage will increase the Collector current. The VCE(sat) is at about 250mV while the specification is for 200mV.

Now do the same measurement with an IC of 50mA and an IB of 5mA.

Set the Step Output to 5mA/Step, Set CH2 to 10mV/Div (10mA), and adjust the offset such that the horizontal line crosses the 5th graticule representing an IC of 50mA.

The point where the vertical line transfers into a horizontal line is the VBE(sat) point. Here at about 250-300mV.

This concludes all the measurements out of the handbook for a Bipolar Transistor.

 

More measurements for other devices may be added later.

 

 

3. Testing transistor breakdown parameters

Apart from the measurements we just saw earlier, described in the Tektronix handbook, there are a lot more we can make to profile a BJT.

I'm going to follow a list of measurements as they are described in the ON semi AN1628/D Application note for high power BJT's. The same principles apply to small signal ones, like the 2N3904.

A link to the app note is listed above.

The nice thing about this App Note is that they included a little schematic of how the DUT is wired for the various measurements and tests.

 

I'm going to follow their measurement order starting on page 12.

 

Breakdown Voltages

BV stand for Breakdown Voltage. This is also shown as V(BR)CEO in some data sheets.

Set the output selector to Tri for Triangle Sweep Voltage waveforms.

BVCEO 

This measurement is for reverse Collector to Emitter voltage, with the Base open, under a given Collector current bias.

 

We already did this measurement above, but here it is again, just for completeness. 

Connect the 2N3904 to the DUT socket with only the C to C and E to E leads connected, leave the Base lead open, so flopping in the breeze.

Set the voltage range to 75V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current. Set the Sweep voltage to minimum.

Set CH1 to 10V/Div and CH2 of the DSO to 200uV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow.

The 2N3904 shows this to happen at 60V, the specification is for 40V.

NOTE

What can happen when you make this measurement is a case of a snap-back breakdown, which is common in this configuration. The Base is open and the avalanche current (also called first breakdown) is reaching a critical Base current to cause the device to enter a second breakdown at a lower voltage. The voltage at the Base will depend on the level of current limiting and the amount of resistance from Emitter to GND. I have measured up to 50V on the floating Base lead with a DMM myself.

This effect is described in the App Note on page 4, Second Breakdown.

 

We also found that the breakdown or even the punch-through event can turn on the Fault indicator LED because the protection circuits for the Step Gen are activated as a result of severe glitches generated by the DUT. This event will cause glitches on the Step Gen supply rails and that trips the Fault circuitry and in turn switches the Collector voltage off for a about 16 Milli-seconds and then release it again. The fact that the protection circuit fires does not change the Breakdown Voltage measurement, but it does protect the DUT from harm.

 

BVCBO

This is the reverse Collector to Base voltage, with the Emitter open, under a given Collector current bias.

 

Connect the 2N3904 to the DUT socket with the Collector to C and the Base to the E contact, leave the Emitter lead open, so flopping in the breeze.

Set the voltage range to 75V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 20V/Div and CH2 of the DSO to 200mV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow.

The 2N3904 shows this to happen at 140V, the specification is for 60V.

BVCER

Reverse Collector to Emitter voltage, the Base connected to the Emitter with a low Ohm resistor, under a given Collector current bias.

Connect the 2N3904 to the DUT socket with the Collector to C, the Base with 100 Ohm to E and the Emitter to E. Keep the resistor very close to the 2N3904 and use short leads.

Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 20 or 50V/Div and CH2 of the DSO to 200uV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow.

The 2N3904 shows this to happen at 125V, there is no specification in the data sheet.

 

The current is limited at 400uA.

BVCES

Reverse Collector to Emitter voltage, the Base shorted to the Emitter, under a given Collector current bias.

Connect the 2N3904 to the DUT socket with the Collector to C, the Base and the Emitter to E.

Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 20V/Div and CH2 of the DSO to 200uV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow.

The 2N3904 shows this to happen at 140V, there is no specification in the datasheet.

 

 

 

BVCEX

Reverse Collector to Emitter voltage, with a reverse Base to Emitter bias, under a given Collector current bias.

 

We do not have a calibrated offset voltage so this measurement could be made, but with an external supply.

  

Connect the 2N3904 to the DUT socket with the Collector to C, the Base to a negative variable DC supply, the positive supply connector to the Emitter and the Emitter to E. 

 

BVCEY

Reverse Collector to Emitter voltage, with a forward Base to Emitter bias, under a given Collector current bias.

 

We do not have a calibrated offset voltage so this measurement could be made, but with an external supply. 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base to a positive variable DC supply, the negative supply connector to the Emitter and the Emitter to E. 

BVEBO

Reverse Emitter to Base voltage, with the Collector open, under a given Emitter current bias.

Connect the 2N3904 to the DUT socket with the Emitter to C, the Base to E and the Collector open.

Set the voltage range to 35V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 2V/Div and CH2 of the DSO to 500uV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow.

The 2N3904 shows this to happen at 8.2V, the specification is 6V.

 

 

Leakage Currents

These measurements are the domain of the DC Voltage. Set the voltage selector to DC.

Note that with our CT, and many others, the leakage current measurements are made in the Collector connection to the positive supply, not in the Emitter connection to the negative supply. In the DC mode, you only see a "dot" representing the voltage on the DSO.

ICEO

Collector to Emitter current under reverse Collector to Emitter voltage, Base open.

 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base open and the Emitter to E.

Set the voltage range to 200V, the current range to 0.02 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 20V/Div and CH2 of the DSO to 1mV/Div.

Power the DUT and slowly increase the DC Voltage until current starts to flow.

 

 

The 2N3904 shows this to happen at 82V, when the "dot" changes to a vertical line. The vertical line means that the current is fluctuating wildly. There is no specification for this test in the data sheet.

The amount of current here is about 3.3mA but can be further increased by carefully increasing the CL adjustment.

 

NOTE

What can happen when you make this measurement is a case of a snap-back breakdown, which is common in this configuration. The Base is open and the avalanche current (also called first breakdown) is reaching a critical Base current to cause the device to enter a second breakdown at a lower voltage. The voltage at the Base will depend on the level of current limiting and the amount of resistance from Emitter to GND. I have measured up to 50V on the floating Base lead with a DMM myself.

This effect is described in the App Note on page 4, Second Breakdown.

 

We also found that the breakdown or even the punch-through event can turn on the Fault indicator LED because the protection circuits for the Step Gen are activated as a result of severe glitches generated by the DUT. This event will cause glitches on the Step Gen supply rails and that trips the Fault circuitry and in turn switches the Collector voltage off for a few Milli-seconds and then release it again. The measured voltage is still indicating the maximum.

 

Due to the Fault circuit tripping, you will see something like this on the DSO:

 

There is no "dot" representing the DC voltage, because it switches between zero and the set voltage.

 

 ICBO

Collector to Base current under reverse Collector to Base voltage, Emitter open

 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base to E and the Emitter open.

Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 50V/Div and CH2 of the DSO to 1mV/Div.

Power the DUT and slowly increase the DC Voltage until current starts to flow and the dot goes up. If the limiting stops the voltage from going up, increase it a little.

 

 

The 2N3904 shows this to happen at 150V. The current is limited by the CL at 2mA, but can now be further increased. There is no specification in the data sheet.

 

ICER

Collector to Emitter current under reverse Collector to Emitter voltage, Base connected to Emitter by a low Ohm resistor.

 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base with 100 Ohm to E and the Emitter to E.

Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to50V/Div and CH2 of the DSO to 1mV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow. If the limiting stops the voltage from going up, increase it a little.

 

The 2N3904 shows this to happen at 125V and at 800uA. The current can now be increased further by the CL. There is no specification in the data sheet.

 

ICES

Collector to Emitter current under reverse Collector to Emitter voltage, Base shorted to Emitter.

 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base and the Emitter to E.

Set the voltage range to 200V, the current range to 0.05 and the CL to 10%, to allow a minimum collector current but without limiting. Set the Sweep voltage to minimum.

Set CH1 to 50V/Div and CH2 of the DSO to 1mV/Div.

Power the DUT and slowly increase the Sweep Voltage until current starts to flow. If the limiting stops the voltage from going up, increase it a little.

 

 

The 2N3904 shows this to happen at 125V, with 1mA. The current can now be further increased by the CL. There is no specification in the data sheet.
 

ICEX

Collector to Emitter current under reverse Collector to Emitter voltage with a reverse Base to Emitter bias.

 

We do not have a calibrated offset voltage so this measurement could be made, but with an external supply. 

  

Connect the 2N3904 to the DUT socket with the Collector to C, the Base to a negative variable DC supply, the positive connector to the Emitter and the Emitter to E.

ICEY

Collector to Emitter current under reverse Collector to Emitter voltage, with a forward Base to Emitter bias.

 

We do not have a calibrated offset voltage so this measurement could be made, but with an external supply.  

 

Connect the 2N3904 to the DUT socket with the Collector to C, the Base to a positive variable DC supply, the negative connector to the Emitter and the Emitter to E. 

 

IEBO

Emitter to Base current under reverse Emitter to Base voltage, Collector open.

 

Connect the 2N3904 to the DUT socket with the Collector open, the Base to E and the Emitter to C.

Set the voltage range to 35V, the current range to 0.02 and the CL to 90%, to allow a minimum collector current but without limiting. Set the DC voltage to minimum.

Set CH1 to 2V/Div and CH2 of the DSO to 500uV/Div.

Power the DUT and slowly increase the DC Voltage until current starts to flow.

 

The 2N3904 shows this to happen at 8.3V. I then increased the CL until there was no more limiting and the dot did no go up any further signalling the maximum leakage current. At the same time, I increased the V/Div to 5mV/Div. The maximum leakage current shown is 10mA.  There is no specification for this test in the data sheet. 

 

4. Profiling a high power BJT

 

Testing a high power BJT like the MJL3281A is a little different in a few aspects.

The MJL3281A is a 260V 15A NPN BJT with an hFE between 45 and 150. 

https://nl.mouser.com/datasheet/2/308/1/MJL3281A_D-2316292.pdf

 

It is one of the transistors we used in earlier Collector/Drain supply versions, most notably in the Version 1b.

 

Because this transistor can dissipate up to 200W, we need to be a little careful.

First of all, I switched the current range to x.5 to allow a maximum current of 1A in the 35V range.

I then started with a Base current of 100uA/step. It produced the following result:

 

 

The hFE stays evenly spread with the Collector voltage and Base currents. The gain is 9mA/100u is about 90.

If we go to a higher Base current, like 1mA/step, we get the following result:

The device is not current limited, but only shows 3 steps? This is because the Y-output amplifier output is hitting the 24V supply rail. 

 

This is because I did not change the IC current shunt from the X10 to the X1 setting yet. This is in effect a 10X multiplier and this causes the input signal to hit the supply rail of 24V.

The X10 multiplier is intended for small signal devices to avoid low V/Div settings of the scope.

 

You could also reduce the number of steps to avoid that, in this case, we can only allow 2 steps. 

 

With the X1 setting, you also need to change the Y-channel of the scope to a ratio of 1X to keep the readout consistent. By also increasing the Current Limiter, we can get the full 7 steps displayed again:

 

 

So how does it behave when we apply the maximum VCE0 of 200V?

I set the Base current to 100uA/step, turned the CL adjustment to 100% and set the current limiter to x1, to have the full 100mA in this range at our disposal. I also used the Step delay to reduce the dissipation.

 

 

At higher Base currents, the Collector current is about to shoot up due to the avalanche effect and the device is getting close to the breakdown voltage. The dV/dt effect is more noticeable with this measurement.

Be careful testing the temperature of the device with your fingers, there is 200V on the collector pad. Keep fingers on the plastic! However, with 100mA, it should not get very warm. Also, make sure you select the right current setting and use the current limiter to protect the device.

 

5. Profiling a small signal MOSFET

 

I'm using the LP0701 in the TO-92 package, which is a P-channel MOSFET. It has a VGS(th) of -1V, a DSS of -16.5V, an RDS(on) of 1.5 Ohm and an ID(on) of -1.25A. So how do we go about testing that device.

 

First of all, the polarity should be P, and this will take care of all the negative polarities of the specifications. It is also a V(oltage) device, so select FET as the device type. We'll select 7 steps. The VGS(th) is 1V, so we'll select 500mV/step to get over the threshold, and a 10V sweep voltage. 

 

Because a MOSFET can conduct a large current, even though it is considered a small signal device, we set the current range to X.1 for a maximum of 200mA and set the CL to 50% so we have a safe maximum of 100mA. We also need to set the Y-amp multiplier to X1 and change the DSO channel multiplier to 1x, not the 0.1x we used for the small signal current devices.

 

Slowly raise the CL limiter to 100%.

 

So what do we see?

 

 

Not what we expected, right? We see only two steps and the rest is current limiting at 200mA. The reason is that with 500mV/step, the device is conducting a lot more current with the higher steps than you would expect from a small signal device.

 

Lower the CL setting first and then switch to a higher current range of X.2 which will be 400mA.

Slowly turn up the current limiter and observe the display. Turn it down quickly to avoid too much heat.

 

This is more like it, but we till can't see the higher steps because of the large Drain current that is limited at 400mA.

 

We need to lower the volts per step, so we'll go down in current. 

At 200mV/step, things start to look a bit more familiar:

 

 

However, we still only see steps 4, 5, 6 and 7. Why? Because step 4 will be at 4*200mV which is the VGS of 1V, when the device starts to conduct so that's the first step we'll see. Steps 1-3 are hidden from view.

How can we look at all the 7 steps? We need to go to an even lower step voltage so now we select 50mV/step to help keep the current in check.

 

We now can use the Step offset feature to put the zero(!) step at the VGS(th) of 1V. We select the negative offset polarity (P-FET) and carefully adjust the offset to display all 7 steps.

You may have to raise the current limit to show all 7 steps without limiting, but turn it down again when you have seen this to keep the device from over-heating.

 

 

 

The zero step is now positioned at a voltage of about 1V, so the steps will further open up the device a step-at-a-time. The beta is increasing with the Drain voltage, something to be aware of. Note that the Drain current is almost at 250mA with step 7. You can use your fingers to keep an eye on the temperature of the device.

To keep the device from over-heating, we can use the step cycle delay function that greatly helps to limit the dissipation. Turn it on, and set it to the maximum. Watch the display and keep your fingers on the device to "feel" the difference.

Let's now see what the Breakdown Voltage (BVDSS) is. This is the voltage at which the reverse-biased body-drift diode breaks down and significant current starts to flow between the Source and Drain by the avalanche multiplication process. Turn up the Drain voltage until the device starts to show this process.

 

At about 20V, you can see that the Drain current is rapidly increasing due to the avalanche effect and is approaching the breakdown voltage. The specification of 16.5V is easily met. The fact that you see oscillation can be part of this particular measurement. The device is getting more and more unstable. 

 

At this voltage level and because the FET is fully conducting, the device will get very hot, so be quick, and be careful. Because of the RDS(on) of only 1.5 Ohm, even the step cycle delay feature will not reduce the thermal heat enough for a long measurement when you use all steps. Make sure you use the right current range and use the current limiter to protect the device from damage or destruction.

 

A more prudent method for determining the VDss Breakdown Voltage is to use only one step, and use the offset feature to just turn the device on, and then increase the Drain voltage to keep dissipation under control.

 

6. Profiling a high power MOSFET

 

One of the power devices I used was out of the small selection of suitable N-MOSFET's we picked for the Collector/Drain supply, the STW6N90K5, a 900V 6A device that has a Vgs(th) of 4V and a Ciss of 432pF.

Select the FET device type.

 

To get a handle on the Gate voltage, you really need to use the offset feature that allows you to set the proper Base step voltage to turn the device on.

 

Here is a screenshot taken with 100mV/Step, 7 steps, 10V and a bit of positive offset to make the zero step already conduct the device.

 The device is getting a tiny bit warm.

To test it with a higher voltage, and keep the dissipation in check, I reduced the number of steps to 4. I used the 75V range with the maximum voltage.

You can see that the gain no longer climbs up after the voltage is at about 40V, this is a much better operating area for this device. Notice the beginning of blossoming of the higher step traces due to the increase in heat.

In the 200V range with maximum voltage, this is the result.

There is current limiting in effect due to the dissipation that I wanted to keep in check, even with a mere 100mA. The device gets hot and the curves start to drift up.

To counter that, you can use the step cycle delay function.

Even with the step cycle delay activated at the maximum delay, the curves still drift upwards, a sign that it still gets hot quickly. Note the beginning of blossoming due to the difference in temperature with the triangle waveform going up, and then down. This is a very typical effect caused by thermal heat.

When you need to make longer measurements with these kind of power devices, it may be wise to add a heat sink to it and/or use a fan to keep it from a runaway-thermal effect that could damage or even destroy the device.

With a specification of 900V for the VDSS, we cannot do the Breakdown Voltage test with the maximum of 200V that is at our disposal.

7. Depletion Mode MOSFET's or J-FET's

JFET's are a special breed in the MOSFET family. In the reference documents at the very top of the page, you can see the difference between depletion mode FET's and enhancement mode FET's. Here is a quick overview from the document I listed.

"Unlike enhancement-mode transistors, which are “normally-off” devices, depletion mode MOSFETs are “normally-on”. N-channel devices are built with P-type silicon substrates, and P-channel versions are built on N-type substrates. In both cases they include a thin gate oxide situated between the source and drain regions. A conductive channel is deliberately formed beneath the gate oxide layer and between the source and drain by using ion-implantation. By implanting the correct ion polarity in the channel region during manufacture determines the polarity of the threshold voltage (i.e. -VTH for an N-channel transistor, or +VTH for an P-channel transistor). The actual concentration of ions in the substrate-to-channel region is used to adjust the threshold voltage (VTH) to the desired value. Depletion-mode devices are a little more difficult to manufacture and their characteristics harder to control than enhancement types, which do not require ion implantation."

JFET's are typically used in high quality audio designs, VHF/UHF amplifiers and fast switches, but also have been used in Automatic Gain Control (AGC) circuits for oscillators, to replace the original lamp bulbs. In this case they are used as a variable resistance device. JFET's are a special breed and many of the earlier types are no longer available. Worse, they pre-dated the internet so there is little or no information available anymore. When there even is a datasheet, they are typically lacking in information and sometimes contain no I/V diagrams. On top of that, due to the manufacturing process difficulties, even devices from the same batch have wildly different specifications. (we have been spoiled over the last decades)

There are a few important characteristics that set an JFET apart from other devices, and that poses a challenge based on how we decided to construct our CT. Let me explain. One of the features or characteristics of a JFET is that the device is normally "on", meaning there is the "maximum" current flow (IDSS) from Drain to Source when the Gate is flopping in the breeze or at the same level as the Source. As a matter of fact, when you connect the Gate to the Source, a constant current flows, regardless of the VDS. This is at the so called pinch-off voltage, or VP. That's actually another application for these devices.

The difference in measuring J-FET's

Remember the difference with other devices. For normal N-type devices, we use the Step Generator by increasing the current or voltage with positively going steps towards "fully opening"  the device, so going for maximum current. With a N J-FET, the device is already open, so we use the Step Gen steps to gradually "close" the device towards zero current by using negatively going steps to reach VGS=0 where the IDSS current is 0 and there is no current flow.

The pinch-off voltage (Vp)

The Pinch-off voltage is the specific gate-source voltage (VGS) level at which a JFET enters saturation and the channel becomes effectively 'pinched off.' This point marks the transition from the linear region to the saturation region of operation, where the FET maintains a constant current regardless of increases in drain-source voltage. When the gate-source voltage exceeds the pinch-off voltage, the depletion region widens, effectively reducing (pinching) the channel size and limiting the current. 

Our VBA Curve Tracer works a little different for JFET's

I made the decision a long time ago to make the operation of our CT as simple as possible, and that meant that the StepGen only produces positive currents and voltages for N-type devices, and negative currents and voltages for P-type devices.  However, as we have just seen, N-type JFET's require negatively going steps (-VGS) , which we don't support. (we could but we don't)

Using a traditional CT and the VBA CT

Have a look at the Tektronix document I added at the top of this post for a reference. It explains how you test a JFET for a small signal forward transfer admittance, or the ratio of change in ID to a change between two VGS steps. That ratio is also called the small signal gain.

Because the Tektronix CT's do not have a coupled measurement system as we do, to make it more simple to use for most users, we need to go about it in a slightly different way. The traditional way is to align the 0 step with the IDS trace on the display by vertical movement of the V/Div setting. The IDS trace is the result of the JFET being fully open (by default). You then apply a negatively going second step, and measure the voltage difference (current) between the two curves. 

With our CT, we apply the -VGS voltage with the negative offset feature, so there is no more current flowing. IDS=0. We than apply one or more positive going steps (opening up the device, not closing the device) so you can measure the same difference between two curves and arrive at the same conclusion.

However, there may be one more complication.
Our normally recommended offset range is +/-2V, which is sufficient for most applications and many JFET's. However, there are a number of JFET's where the -VGS-off is significantly higher. I have one that needs a VGS of -5V. The J111 can be up to -10V. Luckily, there is a documented modification for the CT that can be made that will change the offset range all the way up to +/-10V. If you are regularly measuring these types of JFET's I suggest you change the offset range for your instrument, and also use the optional multi-turn potmeter for the offset.

My CT currently has the +/- 2V offset range, so I use a "trick" to reach the -VGS-off by using a Lab power supply connected to the 2mm E/S and B/G connectors in the reversed mode, to supply a negative VGS. In addition, you can also use a DMM to measure that voltage so you get an accurate reading of the VGS-off voltage.

2N4391 N-JFET

As an example, I will demonstrate this measurement with the 2N4391 N-JFET from Central Semiconductor Corp. I have two of the older versions, newer ones are only available with the "PBFREE" manufacturing process. 

BTW, the versions I have now will cost you $18,25 a piece at DigiKey, and they have no stock for this part at all. Mouser has the PBFREE version for 3,03 Euro's with 2,500 in stock and LCSC has currently no stock but normally sells the PBFREE version for $3,76.

The specification for VGS-off has a wide range in the datasheet, so here is how you measure that. 

The JFET is inserted into the test socket. The CT settings are: DUT Select off, Voltage at 0%, 35V range, 0.2x current range, Current Limit (CL) set at 40%, Polarity to N, BJT/FET to the FET position, Offset off, Step Delay off, number of steps to 0, and the Step Output to 500mV/step.

Select the proper DUT socket and slowly turn-up the Drain supply. You will see a curve that looks like the one below:

We see that the device starts to conduct at a VDS of 0V and current moves up in a pretty linear fashion up to about a VDS of 2V and an IDSS of 40mA. This is the Lineair region that is interesting for the variable resistor applications, like an ACG circuit. At about a VDS of 6 volt the device has reached the maximum current of almost 60mA (now in the Saturation region) and that stays pretty flat all the way to the maximum VDS.  The transition from the liniar to the saturation region is at the pinch-off (VP) voltage, another other interesting feature that can be used in a constant current application. BTW, the device has a negative temperature effect, so heating up will reduce the current. No possible thermal run-off with JFET's. Note that the device can get pretty hot, so keep an eye on the temperature and keep measurements short.

By setting the number of steps to 0, we actually let the Gate float to it's internally determined voltage. 

I measured the VGS to be about 1.21V on one device and 1.88V on the other. This value slowly drops down while the device is heating up due to the IDSS current flow. You can also see that by the curve dropping down a bit.

To measure the zero current point, -VGS-off, we need to apply a negative offset to the Gate. Turn the Offset potmeter to minimum, and select the Neg offset position. Slowly turn the offset from min to max, and you will see the curve flatten downwards. We do not have a calibrated offset voltage measurement, so you can hook-up a DMM between the Source and the Gate. (I use the 2mm sockets for that hook-up)

With my CT, I can only go down to a VGS of -2V, so I can't turn the device fully off, shown by a flat line, so I use my Lab Supply in a reverse hook-up. The positive lead to Source and the negative lead to the Gate. Set the maximum current of the Lab Supply to 70mA (because it needs to sink the current) and start with 0 volts. Turn the supply on, and slowly increase the voltage while looking at the curve until it flattens and there is no IDS current flowing anymore. Note the voltage on the DMM because that is the -VGS-off for that particular device. I measured a VGS of -4.7V on one of my devices, the other one measured -5.1V. De-select the device socket to prevent self heating.

It is allowed to excite the device a little more than the "natural" current, by applying a voltage a little higher than the "natural" VP with a positive VGS. We help that a bit by first lowering the VGS with the offset. Set the Step Output to 500mV/Step. Because the IDSS will go up, you need to select the x.2 current range and set the CL to 40%. 

Set the offset to Neg and turn the offset to maximum (I used -2V) and select the device socket. Slowly select a higher number of steps to 4 and you will see the more familiar stepped I/V curves. 

BF256B N-JFET

This is a typical JFET used in VHF/UHF amplifier applications.

Nota that this device has a much lower constant current (11mA) compared to the 2N9341.

With the maximum offset of VGS at -2.1, the device almost reaches the VGS-off, it needed -2.8V to fully turn off. I also applied 4steps of 500mV/Step. Note the rumble on the traces due to the sensitivity of the DSO setting at 2mV/Div.

2N5754 N-JFET

This is a JFET for audio and fast switching applications.

It has an even lower constant current of almost 3mA. This device also has a lower VGS-off, so with my CT, I could fully turn it off by applying an offset of -1.5V.

With the input at 500uV/Div, my DSO now shows even more rumble.

Tektronix 151-1021-00 N-JFET

This is a special case and the reason for taking these measurements. This NFET is used in many Tektronix instruments and is no longer available. In the Tek manuals, it is listed as a Siliconix, Inc. FN815. Unfortunately, there is no trace of any documentation I could find. So there is quite a hunt for alternatives going on.

I also use this part in two of my projects, the DIY rebuild of the SG502 a while ago and currently the SG505 oscillator. The SG502 was finished a number of years ago and I have just started a Blog post about the SG505 instrument. This JFET is used in the AGC circuit for the oscillator, a very critical circuit because the very low level of THD is depending on this circuit.

I'm a lucky person to have two devices, saved from the late 70's up until now, with one in my SG502, and one destined to go in my SG505. However, the unobtanium status of this JFET will stop others from building my project as well, so I have started a little search project to find a suitable replacement that is more commonly available, active and for a decent price.

So this is the brand-new, never used 151-1021-00 JFET showing it's mysteries.

The slope is not very steep, and not very linear either. This means that in this particular application, using it as a variable resistor, the VDS voltage must be kept very low. The current is quite substantial at 65mA. It needs a VGS of -5.2V to fully turn it off, quite a lot actually.

So, if you want to use this device in an Automatic Gain Control (AGC) circuit, the slope is important, so I've zoomed in a bit more.

The curve is pretty linear all the way up to about 2VDS, so the lower that voltage is, the better the linearity is. Notice the very slight blooming of the trace with higher currents, an indication of the self-heating due to the current flow.

If we add 3 steps at 500mV/Step with the maximum -2V offset, we will get this: 

Note that the blooming is now even more visible due to the higher currents.

If you now look with the same settings again to the 2N4391, it looks very close to the 151-1021-00 part.

I need to do some more tests, but this looks like a decent replacement that is available and still active.

 

More measurements may be added later...